Multi-depth Polycrystalline Isolation for Semiconductor Leakage
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Solution Overview
Problem
Semiconductor device structures, such as radiofrequency switches, face challenges with high capacitance and body-to-body leakage when using bulk semiconductor wafers, necessitating improved electrical isolation methods.
Innovation Solution
The implementation of shallow trench isolation regions and a polycrystalline layer within the semiconductor substrate, formed through ion implantation and annealing, provides enhanced electrical isolation by creating distinct depth sections beneath the active device region and isolation regions, reducing leakage and improving substrate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a polycrystalline layer is formed at a uniform depth beneath the top surface, then the formation process is simplified, but electrical isolation between the active device region and the substrate is insufficient
Solution Approach 1:
The patent applies local quality by creating a polycrystalline layer with non-uniform depth characteristics. Specifically, the polycrystalline layer has a first depth beneath the top surface in the active device region and a second, greater depth beneath the shallow trench isolation regions. This localized depth variation provides enhanced electrical isolation where needed (under the isolation regions) while maintaining process simplicity through a single ion implantation and annealing sequence.
2Reliability
If shallow trench isolation regions are used to reduce body-to-body leakage, then electrical isolation is improved, but substrate leakage remains insufficiently reduced
Solution Approach 1:
The patent applies dimensionality change by extending the isolation mechanism from the lateral dimension (shallow trench isolation regions) into the vertical dimension. The polycrystalline layer is formed at different depths beneath the top surface, with greater depth beneath the shallow trench isolation regions. This vertical depth variation creates a three-dimensional isolation structure that effectively blocks substrate leakage paths while maintaining lateral isolation functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces substrate leakage and enhances device performance by acting as an isolation layer between the field-effect transistor and the bulk substrate, improving electrical isolation and substrate resistance.
Implementation Method 1
A single ion implantation is performed into the semiconductor substrate that produces a band of implanted inert ions beneath the top surface of the semiconductor substrate and that damages single-crystal semiconductor material in an implanted region between the top surface of the semiconductor substrate and the band of implanted inert ions
Implementation Method 2
The semiconductor substrate is recrystallized in the implanted region and the band of implanted inert ions with an annealing process to produce a polycrystalline layer in the semiconductor substrate
Data Source
AI summary
Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.