Polycrystalline Oxide TFT Structure for High-Voltage Reliability

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Solution Overview

Problem

Thin film transistors using oxide semiconductors deteriorate due to high-voltage application between the source and drain, leading to reduced reliability such as a shift in threshold voltage.

Innovation Solution

A semiconductor device configuration with a polycrystalline oxide semiconductor layer having distinct regions of varying electrical resistivity, including a low-resistance conductive region and a high-resistance LDD region, is designed to enhance reliability by suppressing impurity implantation and hydrogen diffusion, with a gate insulating layer and buffer layer to protect the oxide semiconductor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-voltage is applied between source and drain to improve device performance, then field-effect mobility increases, but reliability deteriorates due to threshold voltage shift

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidfield-effect mobility
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The oxide semiconductor layer is divided into regions with different resistivities: a high-resistivity region (≥1×10^12 Ω·cm) under the gate electrode for stable threshold voltage, and a low-resistivity region (<1×10^12 Ω·cm) in the source/drain contact areas for high field-effect mobility. This local differentiation resolves the contradiction between reliability and productivity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The oxide semiconductor layer is segmented into multiple functional regions with distinct electrical properties. The high-resistivity channel region prevents impurity diffusion and maintains threshold voltage stability, while the low-resistivity source/drain regions enable efficient charge transport, thus achieving both high reliability and high productivity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the oxide semiconductor layer is made highly conductive to improve field-effect mobility, then device performance increases, but etching resistance decreases

Engineering Contradiction:
Improvefield-effect mobilityVSAvoidetching resistance
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

Different regions of the oxide semiconductor layer have different resistivities tailored to their functions. The source/drain regions have low resistivity (<1×10^12 Ω·cm) for high field-effect mobility, while maintaining sufficient etching resistance through controlled composition and thickness. The channel region has high resistivity for stability. This local quality differentiation resolves the contradiction between conductivity and etching resistance.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If a simple-structure low-temperature process is used to form the thin film transistor, then manufacturing complexity decreases, but device reliability deteriorates

Engineering Contradiction:
Improveprocess simplicityVSAvoiddevice stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The invention uses parameter changes in the oxide semiconductor layer (resistivity, thickness, composition) to achieve high reliability without requiring complex high-temperature processes. The layer is formed at low temperatures but achieves superior electrical properties through controlled oxygen content and crystalline structure, resolving the contradiction between ease of manufacture and device reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250113542A1Semiconductor device
Publication Date: 2025.04.03 JAPAN DISPLAY INC
  • US20250113542A1 patent drawing
  • US20250113542A1 patent drawing
  • US20250113542A1 patent drawing

AI summary

A semiconductor device comprises a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the semiconductor oxide layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. An electrical resistivity of the second region is higher than an electrical resistivity of the first region and lower than an electrical resistivity of the third region. A sheet resistance of the third region is less than 1000 ohm/square.