Polycrystalline Display Pixel Circuit for Low-Frequency Flicker

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Solution Overview

Problem

Existing light emitting display devices experience flicker when driven at low frequencies due to high leakage currents, which are exacerbated by the use of polycrystalline semiconductors.

Innovation Solution

The light emitting display device incorporates transistors with channels in a polycrystalline semiconductor layer, where the width and length of the channels are specifically designed to minimize leakage current, and a gate insulating film with a controlled thickness is used to further reduce leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polycrystalline semiconductors are used in light emitting display devices, then manufacturing complexity is reduced and device performance is improved, but leakage current increases causing flicker at low frequencies

Engineering Contradiction:
Improvedisplay stabilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies parameter changes by precisely controlling the channel width and length dimensions of the transistor, as well as the thickness of the gate insulating film. These parameter adjustments optimize the balance between leakage current reduction and manufacturing simplicity, allowing the use of polycrystalline semiconductors without excessive flicker at low frequencies

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If channel width and length are reduced to minimize leakage current, then flicker is reduced, but transistor driving capability may be compromised

Engineering Contradiction:
Improveleakage currentVSAvoidtransistor driving capability
Core Design Contradiction:
Object-generated harmful factorsVSPower

Solution Approach 1:

The patent optimizes the channel width and length parameters within specific ranges (channel width: 1-2 μm, channel length: 1-2.5 μm) to achieve the right balance between minimizing leakage current and maintaining sufficient transistor driving capability for proper display operation

Inventive Principle:
Principle #35Parameter changes

3Reliability

If gate insulating film thickness is controlled to reduce leakage current, then display quality improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedisplay qualityVSAvoidfilm thickness control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent specifies a controlled thickness range for the gate insulating film as part of the parameter optimization strategy. This approach improves display quality by reducing leakage current while establishing clear manufacturing specifications that define the required precision level

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows the light emitting display device to operate without flicker even at low frequencies, maintaining display luminance and reducing manufacturing complexity by minimizing the need for additional semiconductor layers.

Implementation Method 1

channels of the second transistor, the first transistor and the third transistor are disposed in a polycrystalline semiconductor layer

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250151521A1Light emitting display device and manufacturing method thereof
Publication Date: 2025.05.08 SAMSUNG DISPLAY CO LTD
  • US20250151521A1 patent drawing
  • US20250151521A1 patent drawing
  • US20250151521A1 patent drawing

AI summary

A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 μm to about 2 μm, and a length of the channel of the third transistor is in a range of about 1 μm to about 2.5 μm.