Polygonal Chip Pad Layout for Dense Packaging and Bond Strength
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity and functionality of chips lead to larger sizes, compromising the lightness and thinness of electronic devices, and the pad packaging process becomes a bottleneck in the industry chain, especially with refined internal wafer packaging at 7 nm.
Innovation Solution
The use of polygonal pads on chip and circuit board substrates with straight sides, reducing the distance between adjacent pads to 0.3 mm, enhancing stress resistance and structural strength, and improving bonding strength with tin balls, thereby reducing the overall size and weight of the chip and electronic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip functions are enriched and circuit complexity is increased, then chip functionality is improved, but chip size increases
Solution Approach 1:
The patent transitions from traditional circular pad layouts to polygonal pad shapes (square, rectangular, hexagonal), effectively utilizing space in different geometric dimensions. This dimensional change in pad geometry allows for more efficient space utilization, enabling increased circuit complexity without proportionally increasing chip area.
Solution Approach 2:
The patent changes the geometric parameters of pads from circular to polygonal shapes with specific side lengths and angles. By optimizing these geometric parameters, the pad packaging density is improved, allowing more pads to be accommodated in the same chip area, thus enabling richer chip functions without size increase.
2Volume of moving object
If distance between adjacent pads is reduced, then chip size is reduced, but stress resistance and bonding strength deteriorate
Solution Approach 1:
The patent employs asymmetric polygonal pad shapes (such as rectangular pads with different length and width dimensions) rather than symmetric circular pads. This asymmetry allows for optimized stress distribution across the pad structure, where the longer sides can better withstand shear forces from solder balls, maintaining bonding strength even when pad spacing is reduced.
Solution Approach 2:
The patent introduces rounded corners or curved edges on polygonal pads, combining the space efficiency of polygonal shapes with the stress-distributing properties of curved geometries. This hybrid approach maintains structural integrity and stress resistance while achieving compact pad layouts with reduced spacing.
Data Source
AI summary
The present disclosure relates to a chip, a circuit board and an electronic device. The chip includes a chip substrate and a plurality of pads arrayed on the chip substrate. At least one of the plurality of pads on the chip is a polygonal pad.