Polygonal Chip Stacking With Seal Rings for Compact 3D Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging techniques for semiconductor devices, particularly in achieving smaller form factors, higher integration density, and lower power consumption, which existing methods struggle to address effectively.
Innovation Solution
A method for fabricating stacked semiconductor devices involves forming multiple chips with different polygonal profiles, electrically coupling them, and using seal ring structures to enhance bonding and reduce stress, while employing photolithographic and metallization processes to create conductive contacts and interconnects, and through-silicon vias for efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but form factor reduction and integration density are limited
Solution Approach 1:
The patent divides the semiconductor device into multiple separate chips (first chip, second chip, third chip) with different polygonal profiles, which are then stacked vertically. This segmentation allows each chip to be optimized independently while achieving overall miniaturization through the 3D stacked configuration, directly resolving the contradiction between reducing form factor and managing packaging complexity.
Solution Approach 2:
The patent transitions from conventional 2D planar packaging to 3D stacked packaging by bonding multiple chips vertically. The different polygonal profiles (triangle, square, pentagon, hexagon, heptagon, octagon) enable efficient space utilization in the vertical dimension, achieving superior form factor reduction that cannot be accomplished with traditional 2D packaging approaches.
2Quantity of substance
If chip size is reduced to increase integration density, then more chips fit in smaller space, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric polygonal profiles for different chips in the stack (triangle for first chip, square for second chip, pentagon for third chip, etc.). This asymmetric design with varying numbers of sides creates distinct identification features that simplify alignment and bonding processes, thereby reducing manufacturing precision requirements despite the small chip sizes and high integration density.
Solution Approach 2:
Each chip is assigned a specific polygonal profile with particular local geometric characteristics (number of sides, corner configurations). These localized quality differences in chip geometry enable simplified bonding alignment and reduce the overall manufacturing precision burden, while still achieving high integration density through the compact stacked arrangement.
3Volume of moving object
If multiple chips are stacked to reduce form factor, then integration density increases, but stress management becomes more difficult
Solution Approach 1:
The asymmetric polygonal profiles of stacked chips create natural mechanical interlocking features and distribute bonding stress more evenly across the stack. The varying corner configurations and side lengths of different polygonal chips prevent stress concentration at identical locations, facilitating effective stress management in the compact 3D structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, high-density semiconductor devices with reduced power consumption and improved packaging efficiency, allowing for more compact and high-performance semiconductor devices.
Implementation Method 1
an etching machine to etch the substrate by plasma to form a plurality of trenches
Implementation Method 2
a spin coater to coat the protection layer over the plurality of chips and the plurality of trenches
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes a first chip and a second chip. The second chip is bonded over and electrically connected to the first chip. The second chip includes a seal ring disposed at a periphery of the second chip and within the second chip. From a top view, the second chip includes a first number of sides and the seal ring includes a second number of sides. The first number is greater than four, and the second number is equal to or greater than the first number.