Polygonal Measurement Marks for PCB Layer Registration
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Solution Overview
Problem
Current methods for assessing layer-to-layer registration in multilayer printed circuit boards are time-consuming, costly, and sometimes limited by the availability of test coupons, which hinders accurate electrical characterization.
Innovation Solution
A multilayer printed circuit board design that includes overlapping measurement mark areas on conducting layers, with polygonal measurement marks positioned along angle bisectors for precise alignment, allowing for non-destructive measurement of layer-to-layer registration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If destructive analysis by cross cutting test coupons is used to measure layer-to-layer registration, then measurement can be performed, but it is time consuming, costly, and limited by test coupon availability
Solution Approach 1:
The patent creates optical copies (images) of measurement marks on different layers and performs registration measurement on these copies rather than physically cutting test coupons. The measurement system captures images of alignment marks through the multilayer board and processes them computationally, eliminating the need for destructive physical analysis.
Solution Approach 2:
The patent replaces the mechanical destructive analysis method (cross-cutting test coupons with a knife or saw) with an optical measurement system. Instead of physically sectioning the board to view internal layers, the system uses optical imaging to non-destructively capture and measure the positions of alignment marks on different layers.
2Measurement precision
If destructive analysis by cross cutting test coupons is used to measure layer-to-layer registration, then measurement can be performed, but it is costly and limited by test coupon availability
Solution Approach 1:
The patent creates optical copies (images) of measurement marks on different layers and performs registration measurement on these copies rather than physically cutting test coupons. The measurement system captures images of alignment marks through the multilayer board and processes them computationally, eliminating the need for destructive physical analysis.
Solution Approach 2:
The patent introduces an optical intermediary system that allows measurement without direct physical access to internal layers. The optical system acts as a mediator, transmitting information about the positions of alignment marks from deep within the multilayer structure to the surface where imaging occurs, eliminating the need to physically extract or section test coupons.
3Quantity of substance
If narrower line width and spacing are used in packaging substrate, then circuitry density increases, but layer-to-layer registration becomes larger than line width and spacing
Solution Approach 1:
The patent divides the measurement task into multiple discrete alignment marks positioned at different locations and orientations on each layer. Instead of relying on a single registration reference, multiple segmented marks provide redundant measurement points that can independently verify registration accuracy, enabling detection of subtle misalignments that would be critical at narrow line widths.
Solution Approach 2:
The patent extends registration measurement from simple two-dimensional planar alignment to three-dimensional spatial measurement by incorporating vertical layer separation into the measurement model. The system measures not only horizontal positions but also accounts for the depth/layer dimension, enabling precise registration control across multiple stacked layers with narrow features.
Data Source
AI summary
Embodiments of present invention provide a multilayer printed circuit board. The printed circuit board includes a first conducting layer (CL) having a first measurement mark area (MMA) and a second CL having a second MMA. A first polygonal measurement mark (MM) in the first MMA and a second and a third polygonal MM in the second MMA, wherein the second polygonal MM is positioned along an extended first angle bisector bisecting a first vertex of the first polygonal MM and a first vertex of the second polygonal MM is substantially aligned with the first vertex of the first polygonal MM, and wherein the third polygonal MM is positioned along an extended second angle bisector bisecting a second vertex of the first polygonal MM and a first vertex of the third polygonal MM is substantially aligned with the second vertex of the first polygonal MM.