Polygonal Wafer-Handling Chamber for Semiconductor Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional semiconductor-processing apparatuses face limitations in productivity and throughput due to long wafer-handling times and inefficient use of reaction chambers, leading to dead time and reduced operational efficiency.

Innovation Solution

A wafer-processing apparatus with eight or ten reactors arranged in four or five discrete units, featuring two wafer-handling robot arms with multiple end-effectors and a polygonal wafer-handling chamber, allowing simultaneous unloading and loading of wafers across all units, along with discrete gas and electric boxes for optimized gas and electric control, enabling continuous operation and reduced dead time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple reaction chambers are used to increase throughput, then productivity is improved, but device complexity increases and dead time occurs when robots wait for chambers to complete processing

Engineering Contradiction:
ImprovethroughputVSAvoidapparatus complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The apparatus is divided into multiple independent dual-chamber modules (first module with chambers 1004A and 1004B, second module with chambers 1006A and 1006B, third module with chambers 1008A and 1008B) that can operate simultaneously. Each module is a self-contained processing unit with its own pair of reaction chambers, allowing parallel processing of wafers without requiring a single complex centralized chamber system.

Inventive Principle:
Principle #1Segmentation

2Productivity

If wafer-handling time is reduced to increase throughput, then productivity is improved, but the robot waits for reaction chambers to complete processing, creating dead time

Engineering Contradiction:
ImprovethroughputVSAvoiddead time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system enables continuous operation by having multiple dual-chamber modules processing wafers in parallel while the wafer-handling robot simultaneously loads and unloads wafers from all modules. The robot performs useful actions (loading/unloading) during the entire processing cycle without idle waiting time, as other modules are completing their processing cycles at different stages.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The wafer-handling robot prepares and positions wafers in advance for loading into reaction chambers before the previous wafers complete processing. The system pre-positions wafers and coordinates timing so that loading operations are ready to occur immediately when chambers become available, eliminating idle time between processing cycles.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If three sides are used for attaching chambers to maximize chamber utilization, then productivity is improved, but the wafer-handling robot is not fully and continuously in operation

Engineering Contradiction:
ImprovethroughputVSAvoidrobot operation efficiency
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The system transitions from a two-dimensional arrangement of chambers on limited sides of the wafer-handling chamber to a three-dimensional configuration where multiple dual-chamber modules are arranged in space around the robot. This allows the robot to access and service multiple modules simultaneously from different directions, fully utilizing its multi-axis movement capabilities and end-effectors to load and unload wafers from all modules in parallel.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10707106B2High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules
Publication Date: 2020.07.07 ASM IP HLDG BV
  • US10707106B2 patent drawing
  • US10707106B2 patent drawing
  • US10707106B2 patent drawing

AI summary

A wafer-processing apparatus includes: multiple discrete units of reactors disposed on the same plane; a wafer-handling chamber having a polygonal shape having multiple sides corresponding to and being attached to the multiple discrete units, respectively, and one additional side for a load lock chamber; a load lock chamber attached to the one additional side of the wafer-handling chamber; multiple discrete gas boxes for controlling gases corresponding to and being connected to the multiple discrete units, respectively; and multiple discrete electric boxes for controlling electric systems corresponding to and being detachably connected to the multiple discrete units, respectively, wherein the gas boxes and the electric boxes are arranged alternately as viewed from above under the multiple discrete units, and the electric boxes can be pulled out outwardly without being disconnected from the corresponding units so that sides of the gas boxes are accessible.