Polyhedron Semiconductor Chip Solder Connections

The patent applies preliminary action by forming solder members to extend along the sides of semiconductor chips before the chips are stacked. This pre-formed solder structure ensures reliable connections when chips are assembled, as the solder members are already positioned to bridge gaps and accommodate misalignments between chips, thereby improving connection reliability without requiring complex real-time adjustment mechanisms during assembly.

The patent transitions from traditional planar solder connections to three-dimensional solder members that extend along the sides of polyhedron-shaped chips. This dimensional change allows solder to provide both mechanical support and electrical connection in multiple directions, enhancing reliability by distributing stress and accommodating thermal expansion in three dimensions rather than being constrained to a single plane.

The patent applies segmentation by dividing the TSV formation process into distinct stages: first etching dielectric layers to create initial openings, then etching the chip body to complete the through-via. This segmentation allows each etching step to be optimized independently, with the dielectric etch creating a guide structure that simplifies the subsequent chip body etch, thereby reducing overall manufacturing precision requirements while enabling vertical chip stacking.

The patent uses dielectric layers as an intermediary structure during TSV formation. The dielectric layers are etched first to create a template or guide structure that defines the TSV path. This intermediary structure simplifies the more difficult chip body etching step by providing pre-defined boundaries and alignment references, thereby reducing the precision requirements for the critical chip body etching while still achieving accurate vertical connectivity.

The patent applies universality by using a single solder layer deposition process that simultaneously creates multiple functional elements: solder members extending along chip sides for structural support and side-to-side connectivity, solder ball elements for top-surface connections, and filler material in TSV openings for vertical connectivity. This multi-functional approach consolidates what would otherwise require separate processing steps into one deposition operation, reducing process complexity while achieving comprehensive connection strength and electrical conductivity.

The patent merges the formation of different solder structures (side-extending members, top-surface balls, and TSV fillers) into a single integrated solder layer deposition process. Rather than separately depositing solder for each connection type, the process deposits a unified solder layer that self-organizes into the required structures based on the underlying hole and TSV geometries, thereby reducing process complexity while maintaining strong mechanical and electrical connections.