Semiconductor Package Bump Support Structure for Cold Joint Prevention

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in achieving high-density integration and reliable electrical connections due to limitations in feature size reduction and stress management during thermal cycles, which affect the yield and reliability of semiconductor packages.

Innovation Solution

The implementation of a semiconductor package structure that includes a redistribution layer with alternating dielectric and conductive layers, raised support structures around conductive bumps, and metal pillars for enhanced electrical connections, along with an interposer and encapsulant layer to provide structural support and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If feature size is reduced to achieve higher integration density, then integration density is improved, but manufacturing precision and reliability deteriorate due to stress management issues during thermal cycles

Engineering Contradiction:
Improveintegration densityVSAvoidpackage reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the conductive bump structure into multiple functional layers: a base conductive bump, an intermediate raised support structure, and a top conductive feature. This segmentation allows each layer to independently manage stress and deformation during thermal cycling, preventing failure in high-density configurations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a two-dimensional planar conductive bump to a three-dimensional raised support structure with vertical walls and a top surface. This dimensional change provides additional structural support and stress distribution pathways, enabling reliable electrical connections at reduced feature sizes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If feature size is reduced to achieve higher integration density, then integration density is improved, but manufacturing precision deteriorates due to stress-related defects

Engineering Contradiction:
Improveintegration densityVSAvoidfeature size precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The raised support structure is formed beforehand to provide a pre-engineered stress-absorbing framework before subsequent manufacturing steps. This preemptive structural reinforcement compensates for stress-induced dimensional variations that would otherwise occur during thermal cycling and processing

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent applies different material properties and structural characteristics to different regions: the raised support structure has vertical walls with specific thicknesses for stress resistance, while the top conductive feature has optimized geometry for electrical performance. This localized optimization maintains precision across the entire structure despite overall size reduction

Inventive Principle:
Principle #3Local quality

3Device complexity

If conventional packaging structures are used, then device complexity is maintained at acceptable levels, but electrical connection reliability deteriorates due to insufficient structural support to conductive bumps

Engineering Contradiction:
Improvepackage structure complexityVSAvoidelectrical connection reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The raised support structure is formed in advance before the final conductive bump is completed. This preliminary action establishes a robust structural foundation that prevents subsequent manufacturing defects and ensures reliable electrical connections without requiring complex post-processing steps

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20230395520A1Method of manufacturing semiconductor packages
Publication Date: 2023.12.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230395520A1 patent drawing
  • US20230395520A1 patent drawing
  • US20230395520A1 patent drawing

AI summary

A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer. The die is electrically bonded to the interposer and disposed over the interconnection structure. The conductive terminal is connected to the interposer and the die via a conductive bump. In order to effectively avoid cold joint issues, round or rectangular polyimide structures are first disposed under the bumps to structurally support the bump and sufficiently increase bump height for improved electrical connection and long term reliability of the package structure.