Polyimide PCB Base Material With Low-Void Plated Conductor Layers
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Solution Overview
Problem
Existing printed circuit base materials with polyimide as a main component suffer from voids generated during electroless plating, leading to circuit defects in fine patterns due to conductor peeling and insulation failures.
Innovation Solution
A base material with a conductor layer comprising a metal sintered layer and an electroless plating layer, where voids with a maximum width of 5 μm or more are limited to 10 or less per 0.25 mm², and the base film does not contain palladium, using an electrolysis assist for electroless plating to enhance conductivity and adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroless plating is performed using conventional methods with palladium catalyst, then the conductor layer can be formed, but voids are generated in the base film causing circuit defects
Solution Approach 1:
The invention extracts and removes the harmful element (palladium catalyst) from the electroless plating process. By eliminating palladium, the root cause of void formation in the base film is removed, thereby preventing circuit defects while still achieving conductor layer formation through alternative catalyst-free electroless plating methods
Solution Approach 2:
The invention converts the harmful effect of palladium-induced void formation into a beneficial outcome by developing a palladium-free electroless plating process. This approach not only eliminates the harmful voids but also creates a more reliable conductor layer structure suitable for fine-pattern printed circuits
2Manufacturing precision
If fine pattern conductors are formed on base film, then high precision circuits are achieved, but voids cause peeling and insulation failures
Solution Approach 1:
By extracting the palladium catalyst from the process, the invention eliminates the source of void formation that compromises conductor adhesion. This allows fine pattern conductors to maintain both high precision and strong adhesion to the base film without peeling or insulation failures
Solution Approach 2:
The invention changes the chemical parameters of the electroless plating process by removing palladium and adjusting the plating solution composition. This parameter change prevents void formation while maintaining the ability to form precise fine pattern conductors with adequate adhesion strength
3Ease of manufacture
If electroless plating is performed without controlling void formation, then conductor layer is deposited, but thermal decomposition of base film occurs
Solution Approach 1:
By removing the palladium catalyst, the invention eliminates the localized heat generation and chemical reactions that cause thermal decomposition of the base film during electroless plating. This maintains base film thermal stability while preserving ease of manufacture through simplified process conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Suppresses circuit defects in fine patterns by reducing voids, ensuring reliable conductor adhesion and conductivity, and allowing for precise thickness adjustment of the conductor layer.
Implementation Method 1
depositing, on the first conductor layer, a conductor serving as a catalyst from an electroless plating solution by an electrolysis assist in which an electric potential is applied to the first conductor
Implementation Method 2
a first conductor layer which is a metal sintered layer
Data Source
AI summary
A base material for a printed circuit of the present disclosure includes a base film containing polyimide as a main component, and a conductor layer formed on at least one surface of the base film. The conductor layer includes a metal sintered layer formed on the base film and an electroless plating layer formed on the metal sintered layer, and in the base film, a number of voids having a maximum width of 5 μm or more in plan view is 10 or less per a reference unit area of 0.25 mm2 on a surface of the base film.