Polyimide RDLs for 2.5D Interposer Stress Relief
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Solution Overview
Problem
2.5D semiconductor packages face reliability issues due to thermo-mechanical stress from coefficient of thermal expansion (CTE) mismatches between interposers and substrates/dies, and height differentials between adjacent semiconductor dies, which can lead to damage and functionality issues during manufacturing and thermal management.
Innovation Solution
The use of polyimide-based redistribution layers (RDLs) on interposers to absorb thermo-mechanical stress and techniques such as larger diameter micro-bumps, copper pillars, and etched interposers to equalize die heights, reducing stress and height differentials between semiconductor dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inorganic interposers are used in 2.5D semiconductor packages, then integration performance is enhanced, but thermo-mechanical stress is exerted on conductive interconnections due to CTE mismatch with organic substrate
Solution Approach 1:
A compliant layer is introduced between the inorganic interposer and the organic substrate to act as a stress-absorbing intermediary. This layer has a coefficient of thermal expansion that falls between the CTE values of the inorganic interposer and organic substrate, thereby reducing the CTE mismatch stress transmitted to the conductive interconnections while maintaining the integration benefits of the inorganic interposer.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the interposer structure by incorporating materials with specific CTE values and mechanical properties. The compliant layer is selected to have intermediate CTE and appropriate mechanical compliance, changing the overall stress distribution parameters in the package structure to reduce harm to conductive interconnections.
2Adaptability or versatility
If semiconductor dies of different heights are mounted on the interposer, then functional integration is achieved, but manufacturing reliability decreases due to increased likelihood of damage to taller chips
Solution Approach 1:
The patent introduces a vertical dimension solution by creating a multi-tiered interposer structure with different elevation levels. Taller semiconductor dies are mounted on a first tier at a higher elevation, while shorter dies are mounted on a second tier at a lower elevation. This dimensional approach allows all dies to be at safe heights relative to manufacturing tools while maintaining their functional integration on the same interposer.
Solution Approach 2:
The interposer surface is segmented into multiple tiers or levels, each optimized for mounting dies of specific height requirements. This segmentation allows the manufacturing system to work at a common reference height while accommodating dies of varying heights on different segments of the interposer, thereby maintaining both functional integration and manufacturing reliability.
3Adaptability or versatility
If semiconductor dies of different heights are mounted on the interposer, then diverse chip integration is enabled, but thermal management functionality is inhibited due to inability to share common heat sink
Solution Approach 1:
The multi-tiered interposer structure extends the thermal management solution into the vertical dimension. A common heat sink is positioned to thermally contact both tiers of the interposer through thermal vias and conductive paths, allowing heat from dies of different heights to be dissipated through a unified thermal management system. This maintains diverse chip integration while restoring thermal management functionality.
Solution Approach 2:
The interposer structure itself acts as a thermal intermediary, with thermal vias and conductive pathways that bridge the gap between dies at different heights and the common heat sink. This intermediary thermal path allows heat from both tiers to be efficiently transferred to the heat sink, enabling thermal management for diverse chip integrations with different heights.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polyimide-based RDLs effectively reduce thermo-mechanical stress on conductive interconnections, and the height equalization techniques enhance manufacturing reliability and thermal management by minimizing die height differences, thereby improving the robustness and functionality of 2.5D semiconductor packages.
Implementation Method 1
The polyimide-based RDLs effectively reduce thermo-mechanical stress on conductive interconnections
Data Source
AI summary
Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies.