Low-Temperature Cure Polyimide Redistribution Layer I-Line Lithography
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the physical size of semiconductor devices while maintaining performance, as traditional bonding processes are inefficient and require sophisticated techniques to stack and bond active circuits on separate substrates effectively.
Innovation Solution
The process involves forming vias and redistribution structures using a combination of adhesive layers, polymer layers, seed layers, and conductive materials, with specific exposure techniques to polyimide materials, particularly using I-line wavelength lithography for improved resolution and reduced film loss, to facilitate the stacking and bonding of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional bonding processes are used to stack and bond semiconductor devices, then the physical size can be reduced, but the manufacturing efficiency is poor and sophisticated techniques are required
Solution Approach 1:
The invention divides the semiconductor device into multiple separate substrates (first substrate and second substrate) that are bonded together through alignment marks and bonding processes. This segmentation allows each substrate to be manufactured independently using standard processes, improving manufacturing efficiency while achieving compact stacked configuration that reduces overall device volume.
Solution Approach 2:
The invention introduces alignment marks as intermediary features that facilitate the bonding process between substrates. These alignment marks enable precise registration and alignment during bonding without requiring sophisticated alignment techniques, thereby simplifying the manufacturing process while maintaining compact device dimensions.
2Manufacturing precision
If minimum feature size is reduced to increase integration density, then more components can be integrated, but the bonding and stacking processes become more difficult
Solution Approach 1:
The invention incorporates alignment marks and bonding structures into the substrate design before the bonding process. These preliminary features are formed during standard semiconductor fabrication, enabling subsequent bonding and stacking operations to proceed with simpler, less sophisticated techniques while maintaining high integration density achieved through reduced minimum feature sizes.
3Measurement precision
If I-line wavelength lithography is used for polyimide exposure, then resolution is improved and film loss is reduced, but the process requires specific wavelength control
Solution Approach 1:
The invention specifies using I-line wavelength (365 nm) for polyimide exposure instead of other wavelengths. This parameter change in the lithography process provides improved resolution and reduced film loss for polyimide materials. The specific wavelength requirement is compensated by the availability of standard I-line lithography equipment, balancing the need for precise parameter control with manufacturing practicality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient stacking and bonding of semiconductor devices, improving integration density and reducing physical size while maintaining performance, with enhanced resolution and reduced defects in the redistribution passivation layers.
Implementation Method 1
exposing a first surface of the dielectric layer to light of an I-line stepper
Data Source
AI summary
A method of manufacturing a semiconductor device includes the step of positioning a patterned mask over a dielectric layer. The dielectric layer comprises a low-temperature cure polyimide. The method further includes the steps of exposing a first surface of the dielectric layer through the patterned mask to an I-line wavelength within an I-line stepper, and developing the dielectric layer to form an opening.