Polylithic On-Package Integration for Scalable Server Processors
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Solution Overview
Problem
Developing customized silicon solutions for data centers to achieve high energy-efficiency while minimizing Total Cost of Ownership (TCO) is challenging due to high Non-Recurring Engineering (NRE) costs, long lead times, and evolving workload requirements, making monolithic solutions unsustainable and costly.
Innovation Solution
Implementing a polylithic integration approach with smaller, heterogeneous building blocks such as processor chips, accelerator chips, and memory/network IO chips, interconnected via a scalable network-on-package (NoP) using advanced packaging and interconnect technologies like silicon interposers and Embedded Interconnect Bridge (EMIB), allowing for independent optimization and upgrading of each block without redesigning the entire chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fully-integrated monolithic silicon solutions are developed for each workload class, then customization and optimization for specific workloads is achieved, but scalability and sustainability are compromised due to high NRE costs and long lead times
Solution Approach 1:
The patent divides the monolithic silicon solution into separate functional blocks (CPU cores, accelerators, memory, I/O) that can be independently designed, manufactured, and optimized. These segmented blocks are then integrated on-package to form customized solutions for different workload classes, reducing development complexity while maintaining adaptability.
Solution Approach 2:
The patent creates a universal platform architecture with standardized interfaces and interconnects that can support multiple workload classes. The same base platform can be configured with different combinations of functional blocks to serve various workloads, achieving versatility without requiring separate custom designs for each workload type.
2Adaptability or versatility
If a superset solution with over-provisioned resources is integrated on a large monolithic silicon, then all workload requirements can be met, but cost-effectiveness deteriorates due to high NRE costs and manufacturing complexity
Solution Approach 1:
By segmenting the system into separate functional blocks manufactured on different process nodes, the patent enables independent optimization of each block's manufacturing process. This reduces overall manufacturing complexity and cost compared to fabricating all components on a single large monolithic die, while still providing comprehensive workload coverage through appropriate block combinations.
Solution Approach 2:
The patent changes the manufacturing parameters by producing different functional blocks on different process technology nodes (e.g., CPU cores on 7nm, accelerators on 16nm, memory on 10nm). This parameter change allows each block to be manufactured at its optimal process node, reducing overall manufacturing cost while maintaining the ability to meet diverse workload requirements.
3Use of energy by moving object
If highly customized silicon chips are designed for specific workloads, then energy-efficiency is improved, but Non-Recurring Engineering costs and lead times increase significantly
Solution Approach 1:
The patent performs preliminary actions by pre-designing and pre-optimizing individual functional blocks (CPU cores, accelerators, memory controllers) as standalone components. These pre-optimized blocks can then be quickly assembled into customized solutions for different workloads without requiring complete redesign, thus maintaining energy-efficiency while reducing development lead time.
Solution Approach 2:
Segmentation allows each functional block to be independently optimized for energy efficiency in its specific function. The CPU cores can be optimized for general-purpose computing, accelerators for specific workloads, and memory for high-speed access. This modular optimization achieves system-level energy efficiency without requiring lengthy custom design cycles for each complete system.
Data Source
AI summary
Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.