Polymer Buffer Layer in Interposer Packaging for Dense I/O Routing
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Solution Overview
Problem
The increasing miniaturization of semiconductor dies and the need for higher I/O pad density in packaging pose challenges, such as limited pad numbers due to pitch constraints, solder bridges, and inefficiencies in packaging technologies, particularly in fan-in packages and the waste of defective dies in fan-out packages.
Innovation Solution
The integration of a System on Integrate Chip (SoIC) package bonded to an Integrated Fan-Out (InFO) package, which involves an interposer wafer without active or passive devices, using hybrid bonding and inorganic gap-filling materials to increase I/O pad density and reduce warpage, and the use of polymer layers to absorb stress and improve bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fan-in packaging is used to maintain smaller die sizes and lower costs, then throughput is improved and packaging cost is reduced, but the number of I/O pads is limited due to pitch constraints and solder bridges may occur
Solution Approach 1:
The patent transitions from traditional 2D fan-in packaging to 3D integrated packaging by stacking multiple dies vertically and redistributing I/O pads across different layers. This dimensional change allows significantly more I/O pads to be packaged without increasing the footprint pitch, resolving the contradiction between maintaining small die sizes and increasing I/O pad quantity.
Solution Approach 2:
The patent implements nested packaging by placing multiple dies within a single package footprint, with dies stacked vertically and connected through through-silicon vias (TSVs). This nesting approach allows the package to contain more functional units than a single die could provide, increasing effective I/O pad quantity while maintaining compact dimensions.
2Quantity of substance
If fan-out packaging is used to increase I/O pad density and avoid defective dies, then the number of I/O pads is increased and known-good-dies are packaged, but more underfill or molding compound is needed and the process is more complex
Solution Approach 1:
The patent performs preliminary testing and sorting of dies before packaging, ensuring that only known-good-dies are selected and packaged together. This preliminary action prevents defective dies from being included in the final package, reducing rework and yield loss while simplifying the overall packaging process by eliminating the need for complex defect detection and repair steps.
Solution Approach 2:
The patent uses composite packaging structures combining multiple die types, interposers, and advanced interconnection technologies (TSVs, micro-bumps) within a single integrated package. This composite approach allows flexible configuration of I/O pads and functional units, increasing I/O density while managing complexity through modular design and standardized interfaces.
3Quantity of substance
If the pitch of I/O pads is decreased to increase pad density, then more I/O pads can be packed, but solder bridges may occur
Solution Approach 1:
The patent introduces an interposer as an intermediary substrate between the die and the package substrate. The interposer provides a larger area for I/O pad redistribution, allowing pads to be spaced farther apart on the interposer surface even though the die itself remains compact. This intermediary structure eliminates solder bridges by increasing the effective pitch between adjacent solder joints while maintaining high I/O pad density through vertical stacking.
Data Source
AI summary
A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.