Polymer Bump Gold Layer Semiconductor Chip

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Solution Overview

Problem

Conventional gold bumps on semiconductor chips face issues such as cracking when used with anisotropic conductive films due to thermal expansion coefficient mismatch, leading to potential short circuits and high costs, especially in fine-pitched applications.

Innovation Solution

A semiconductor chip design featuring polymer bumps with a gold layer, which includes a silicon substrate, active devices, dielectric layers, metallization structures, and a passivation layer, with an adhesion/barrier layer and seed layer to support a metal layer, allowing for finer pitches and preventing short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional gold bumps are used with anisotropic conductive films, then electrical connection is achieved, but thermal expansion coefficient mismatch causes cracking and reliability issues

Engineering Contradiction:
Improveconnection reliabilityVSAvoidcrack resistance
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent uses a composite structure consisting of a polymer bump material combined with a conductive metal layer (copper, aluminum, or tungsten) and a gold layer for bonding. This composite approach allows the polymer to provide mechanical compliance and absorb thermal stress, while the metal layers provide electrical conductivity and the gold layer ensures reliable bonding to the anisotropic conductive film, thereby resolving the contradiction between connection reliability and crack resistance.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the material parameters by replacing conventional solid gold bumps with polymer-based bumps that have different thermal expansion coefficients matched to the substrate. The polymer material provides better thermal compatibility, reducing thermal stress and cracking while maintaining electrical connection reliability through the integrated metal and gold layers.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If gold layer on polymer bump is used, then cost is reduced and fine pitch is enabled, but additional manufacturing steps are required

Engineering Contradiction:
Improvemanufacturing costVSAvoidstructure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent segments the bump structure into distinct functional layers: a polymer bump body providing mechanical support and thermal compatibility, a conductive metal layer (copper, aluminum, or tungsten) providing electrical conductivity, and a gold layer providing bonding capability. This segmentation allows each layer to be optimized for its specific function and manufactured using appropriate processes, reducing overall cost and enabling fine pitch applications.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The polymer bump structure serves multiple functions simultaneously: it provides mechanical support, thermal stress management, electrical conductivity (through the metal layer), and bonding capability (through the gold layer). This multi-functionality reduces the need for separate components and manufacturing steps, lowering overall manufacturing cost and complexity despite the layered structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The polymer bump solution reduces the risk of short circuits and thermal cracking while lowering costs by using a gold layer on polymer bumps, enabling more reliable and cost-effective semiconductor chip packaging.

Implementation Method 1

an adhesion/barrier layer on the pad exposed by the opening, over the passivation layer and on a top surface and a portion of sidewall(s) of the polymer bump

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS7582966B2Semiconductor chip and method for fabricating the same
Publication Date: 2009.09.01 QUALCOMM INC
  • US7582966B2 patent drawing
  • US7582966B2 patent drawing
  • US7582966B2 patent drawing

AI summary

A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.