Polymer Chip Socket Via Fabrication
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Solution Overview
Problem
Current methods for fabricating high-density interconnects in chip packaging, such as the 'drill & fill' technique, face limitations in creating diverse via sizes and shapes, leading to reliability issues and increased costs due to rough sidewalls, tapering, and inefficient copper filling processes, which hinder the miniaturization and integration of electronic components.
Innovation Solution
The use of pattern or panel plating technologies to deposit copper via posts within a photo-resist pattern, followed by encapsulation in a polymer dielectric, allows for the creation of varied via shapes and sizes without tapering or dimpling, enabling more accurate and cost-effective fabrication of high-density interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If laser drilling is used to create vias, then via channels can be formed quickly, but the vias exhibit rough sidewalls and tapering that reduce effective diameter and electrical contact quality
Solution Approach 1:
The patent replaces the mechanical/thermal laser drilling process with an electrochemical electroplating process to form via channels. This substitution eliminates the rough sidewalls and tapering inherent in laser drilling, producing vias with smooth, uniform cylindrical channels that maintain consistent diameter throughout their length, thereby resolving the contradiction between fabrication speed and via quality.
Solution Approach 2:
The patent changes the fundamental process parameters from laser-based thermal ablation to electrochemical deposition. By controlling electroplating parameters such as current density, electrolyte composition, and deposition time, the process achieves precise control over via dimensions and morphology, producing uniform cylindrical channels without the dimensional inaccuracies and surface roughness caused by laser drilling.
2Ease of manufacture
If drill & fill methodology is used, then vias can be created through existing processes, but it is difficult to produce high density arrays of vias with different sizes and shapes in close proximity
Solution Approach 1:
The patent utilizes the flexibility of electroplating parameters to create vias of different sizes, shapes, and geometries within the same interconnecting layer. By adjusting current density distributions, mask patterns, and deposition conditions, the process can produce high-density arrays of vias with varied dimensions and morphologies, overcoming the limitations of drill & fill methodology while maintaining manufacturing feasibility.
Solution Approach 2:
The patent applies local quality control through spatially varying electroplating conditions, allowing different regions of the substrate to receive customized via geometries. This enables high-density arrays where each via can be independently optimized for its specific function, achieving both manufacturing ease and geometric versatility simultaneously.
3Ease of manufacture
If copper electroplating is used to fill drilled via holes, then filling can be achieved, but dimpling or overfill occurs that creates difficulties for subsequent via stacking
Solution Approach 1:
The patent performs preliminary actions by first creating the via channel geometry through electroplating before attempting to fill it. The via channels are pre-formed with controlled, uniform dimensions and smooth sidewalls, establishing a foundation that prevents subsequent filling defects such as dimpling or overfill. This preliminary structuring enables precise control over final via dimensions and ensures flat, uniform surfaces suitable for subsequent via stacking.
Solution Approach 2:
The patent replaces the problematic two-step drill-then-fill process with a single integrated electroplating process that simultaneously forms both the via channel walls and the fill material. This substitution eliminates the interface between drilled and filled materials, preventing dimpling and overfill defects while ensuring uniform via geometry throughout, thereby enabling reliable subsequent via stacking.
4Productivity
If laser drilling is used on composite dielectric materials, then vias can be created, but significant tapering and rough side walls occur due to the ablation process
Solution Approach 1:
The patent replaces the thermal ablation mechanism of laser drilling with an electrochemical deposition mechanism. This substitution fundamentally changes how material is removed and replaced, eliminating the rough sidewalls and significant tapering caused by laser ablation of composite dielectric materials. The electroplating process produces via channels with smooth, uniform surfaces that ensure reliable electrical contact and consistent via geometry throughout the dielectric stack.
Solution Approach 2:
The patent changes the physical and chemical parameters of the via formation process from high-energy laser ablation to controlled electrochemical reactions. By adjusting electrolyte composition, current density, temperature, and deposition time, the process achieves precise control over via morphology, producing uniform cylindrical channels with smooth sidewalls that maintain consistent electrical properties throughout their length, thereby resolving the reliability issues caused by laser-induced tapering and roughness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and miniaturization of electronic components by allowing for precise control over via dimensions and shapes, reducing manufacturing costs, and improving the integration of passive components like capacitors and filters within the chip package.
Implementation Method 1
The use of pattern or panel plating technologies to deposit copper via posts within a photo-resist pattern
Implementation Method 2
followed by encapsulation in a polymer dielectric
Implementation Method 3
at least one via in series with a capacitor
Data Source
AI summary
A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through the framework around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.