Polymer Crack Stop Seal Ring in Wafer Level Package

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Solution Overview

Problem

Wafer-level packaging (WLP) processes often result in heat affected zones (HAZ) and micro cracks during die separation, leading to device failure, especially in extreme low-k configurations, and passivation layer delamination, necessitating a solution to prevent or reduce cracking and chipping.

Innovation Solution

A crack stop structure is implemented by etching trenches into the substrate within scribe lines and filling them with a polymer dielectric material, providing additional support and protection against cracking, which includes a polymer dielectric layer coating over the substrate surface to reduce stress and improve solder joint reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If laser grooving and/or mechanical sawing is used to separate dies during WLP manufacturing, then die separation is achieved, but heat affected zones (HAZ) and micro cracks appear resulting in device failure

Engineering Contradiction:
Improvedie separation efficiencyVSAvoiddevice failure rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the substrate by introducing trenches along the scribe lines before cutting. These trenches divide the continuous substrate into sections, allowing the cutting process to occur along pre-defined weak points rather than through the entire substrate structure, thereby reducing crack propagation into the die area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary action by etching trenches and depositing polymer dielectric material along the scribe lines before the actual die separation process. This pre-prepared crack stop structure is in place to intercept and stop cracks before they can propagate into the die during subsequent cutting operations.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If conventional WLP processes are used without crack stop structures, then manufacturing simplicity is maintained, but passivation layer delamination occurs resulting in device failure

Engineering Contradiction:
Improveprocess simplicityVSAvoidpassivation layer delamination
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by introducing crack stop structures specifically along the scribe lines where stress concentration and delamination are most likely to occur, rather than modifying the entire substrate uniformly. The polymer dielectric material is deposited only in the trench regions to provide localized stress relief and delamination prevention.

Inventive Principle:
Principle #3Local quality

3Reliability

If trenches are etched and filled with polymer dielectric material to create crack stop structures, then cracking and chipping are reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvecrack preventionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary material (polymer dielectric) that fills the etched trenches along the scribe lines. This intermediary structure serves as a stress-absorbing buffer that prevents crack propagation while maintaining electrical insulation properties, thereby providing crack protection without requiring fundamental changes to the manufacturing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9679855B1Polymer crack stop seal ring structure in wafer level package
Publication Date: 2017.06.13 QUALCOMM INC
  • US9679855B1 patent drawing
  • US9679855B1 patent drawing
  • US9679855B1 patent drawing

AI summary

Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting.