Polymer-Island Bump Structure for WLCSP Solder Joint Reliability

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Solution Overview

Problem

Wafer-level chip-scale packages face reliability issues due to stress concentration at solder joints during drop impacts, which can lead to failures, particularly in mobile applications where flex between the PCB and chip applies stress to solder joints.

Innovation Solution

A four-layer bump structure is developed, comprising a conductive pad, a passivation layer, a re-distribution layer (RDL) with a via opening, a second polymer layer with an island acting as a stress buffer, and an under-bump metallization (UBM) layer, where the island under the bump relieves stress at the interface between the conductive pad and the RDL via, using materials like aluminum, silicon nitride, copper, polyimide, and multi-layer stacks for enhanced durability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional solder ball bump structure is used in WLCSP, then the packaging achieves wafer-level chip-scale integration, but stress concentration occurs at the solder joint interface during drop impact, leading to reliability failures

Engineering Contradiction:
Improvesolder joint reliabilityVSAvoidstress concentration at solder joint
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The bump structure is segmented into multiple functional layers: conductive pad, passivation layer, polymer layer, RDL, UBM layer, and bump. This segmentation distributes the stress across multiple interfaces rather than concentrating it at a single solder joint, with each layer serving specific mechanical and electrical functions to enhance overall reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bump structure employs composite materials including polymer layers (for stress buffering), metallization layers (for electrical conductivity), and passivation layers (for protection). This composite approach combines materials with different mechanical properties to reduce stress concentration while maintaining electrical performance

Inventive Principle:
Principle #40Composite materials

2Stress or pressure

If the bump pad is made larger to reduce stress concentration, then stress distribution improves, but the area available for other circuit elements decreases

Engineering Contradiction:
Improvestress distributionVSAvoidavailable area for circuit elements
Core Design Contradiction:
Stress or pressureVSArea of stationary object

Solution Approach 1:

The conductive pad is positioned in the central portion of the semiconductor die, utilizing the vertical dimension and central area efficiently. This dimensional arrangement allows adequate stress distribution while preserving peripheral areas for other circuit elements and interconnections

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If a multi-layer bump structure is implemented to reduce stress, then reliability under drop and thermal shock improves, but manufacturing complexity increases

Engineering Contradiction:
Improvedurability under drop and thermal shockVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The polymer layer is formed with a via opening that partially exposes the conductive pad before the RDL is deposited. This preliminary structuring allows the RDL to be completely filled and form an integral via, establishing the stress-buffering configuration before subsequent UBM and bump formation, thereby reducing stress concentration from the outset

Inventive Principle:
Principle #10Preliminary action

4Reliability

If the via opening is completely filled with RDL to form an integral via, then electrical connection reliability improves, but material usage and processing time increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The RDL completely fills the via opening and an RDL via is integrally formed with the bump pad, merging the redistribution layer and via formation into a single continuous structure. This integration eliminates separate via drilling and plating steps, reducing processing time while ensuring reliable electrical connection

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20240290737A1Bump structure and fabrication method thereof
Publication Date: 2024.08.29 MEDIATEK INC
  • US20240290737A1 patent drawing
  • US20240290737A1 patent drawing
  • US20240290737A1 patent drawing

AI summary

A bump structure includes a conductive pad on a semiconductor die; a passivation layer covering a perimeter of the conductive pad; and a first polymer layer on the passivation layer. The first polymer layer includes a via opening partially exposing the central portion of the conductive pad. A RDL is disposed on the first polymer layer and patterned into a bump pad situated directly above the conductive pad. The via opening is completely filled with the RDL and a RDL via is integrally formed with the bump pad. A second polymer layer is disposed on the first polymer layer. An island of the second polymer layer is disposed at a central portion of the bump pad. UBM layer is disposed on the bump pad. The UBM layer covers the island and forms a bulge thereon. A bump is disposed on the UBM layer.