Insulating Polymer Layer Planarization via Mechanical Pressing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor package fabrication process faces challenges in achieving stability and cost-effectiveness due to the difficulty in planarizing insulating polymer layers over conductive patterns, which affects the reliability and efficiency of subsequent processes.
Innovation Solution
A method involving the formation of an insulating polymer layer on a substrate, followed by planarization using a pressure member such as a roller or plate, and patterning to expose conductive patterns, which can be performed in a heated atmosphere to maintain planarity and reduce production costs by avoiding complex chemical mechanical polishing (CMP) processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) process is used to planarize the insulating polymer layer, then planarity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent replaces the chemical mechanical polishing (CMP) process with a purely mechanical pressing method using a pressure member. The pressure member is pressed against the insulating polymer layer to achieve planarity without requiring chemical agents or complex polishing mechanisms, thereby simplifying the fabrication process while maintaining the desired planarity.
Solution Approach 2:
The pressure member used for planarization can be a simple, cost-effective component that does not require the expensive equipment and consumables associated with CMP processes. This disposable or reusable pressure member approach reduces manufacturing costs and process complexity while achieving the same planarity outcome.
2Manufacturing precision
If chemical mechanical polishing (CMP) process is used to planarize the insulating polymer layer, then planarity is improved, but production cost increases
Solution Approach 1:
The patent replaces the chemical mechanical polishing (CMP) process with a purely mechanical pressing method using a pressure member. The pressure member is pressed against the insulating polymer layer to achieve planarity without requiring chemical agents or complex polishing mechanisms, thereby simplifying the fabrication process while maintaining the desired planarity.
Solution Approach 2:
The pressure member used for planarization can be a simple, cost-effective component that does not require the expensive equipment and consumables associated with CMP processes. This disposable or reusable pressure member approach reduces manufacturing costs and process complexity while achieving the same planarity outcome.
3Manufacturing precision
If heating is applied during planarization to maintain planarity, then planarity and soft-baking are improved, but thermal degradation risk increases
Solution Approach 1:
The patent applies heating locally and controllably during the planarization process. The pressure member may be heated to a controlled temperature to facilitate planarization and soft-baking of the insulating polymer layer without exposing the entire wafer to high temperatures that could cause thermal degradation of the semiconductor chips.
Solution Approach 2:
The patent carefully controls the temperature parameter during planarization. By maintaining the heating temperature within an optimal range and controlling the duration of heating, the process achieves planarity and soft-baking benefits while avoiding the thermal degradation that would occur at higher temperatures or prolonged exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the stability and reliability of the semiconductor package fabrication process by ensuring planarity of the insulating polymer layer, reducing production costs, and minimizing thermal degradation of semiconductor chips.
Implementation Method 1
planarizing the insulating polymer layer by pressing the insulating polymer layer downward by using at least one pressure member
Implementation Method 2
The planarizing may be performed in a heated atmosphere to planarize and, at the same time, soft-bake the insulating polymer layer
Implementation Method 3
The planarizing may include locally heating the insulating polymer layer by inductively heating the conductive patterns by applying radio frequency (RF) power
Implementation Method 4
the planarizing may be performed by rolling the at least one roller on the insulating polymer layer to expose at least a part of the insulating polymer layer to discharge the solvent from the insulating polymer layer
Data Source
AI summary
A method of fabricating semiconductor packages includes forming an insulating polymer layer on a substrate to cover a plurality of conductive patterns on the substrate, planarizing the insulating polymer layer by pressing the insulating polymer layer downward by using at least one pressure member, and patterning the planarized insulating polymer layer to expose at least parts of the plurality of conductive patterns.