Polymer-Lined TSV Structure for Stress-Resistant Hybrid Bonding
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Solution Overview
Problem
As semiconductor devices progress to advanced technology nodes, challenges arise in integrating components of different sizes and complex features, particularly for multi-stack structure devices, leading to issues like electrical interference, reliability concerns due to stress concentration, and reduced yield in hybrid bonding.
Innovation Solution
The semiconductor device incorporates a polymer liner between the through substrate via (TSV) and the substrate, along with a barrier and adhesion layer, to address the challenges of electrical interference, reliability, and hybrid bonding yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased to achieve greater integration, then productivity and device performance are improved, but electrical interference between adjacent conductive vias increases and reliability deteriorates due to stress concentration
Solution Approach 1:
A polymer liner is introduced as an intermediary material between adjacent through substrate vias (TSVs). This polymer liner acts as a spacing element that physically separates the TSVs, reducing electrical interference and stress concentration while maintaining compact device geometry. The polymer material provides both electrical isolation and mechanical stress relief, enabling higher device density without compromising reliability.
2Ease of manufacture
If conventional fabrication processes are used for Through Substrate Vias (TSV), then manufacturing simplicity is maintained, but deformation of TSV and stress concentration occur leading to reduced yield in hybrid bonding
Solution Approach 1:
The polymer liner is formed in advance, before the TSV fabrication process, by defining a patterned layer over the substrate. This preliminary action establishes the spacing structure that will guide subsequent TSV formation, ensuring that TSVs are deposited with proper spacing and alignment. The pre-formed polymer pattern serves as a template that prevents TSV deformation during later processing steps and hybrid bonding operations.
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.