Polymer-Lined TSV Structure for Interference and Stress Relief
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Solution Overview
Problem
As semiconductor devices progress to advanced technology nodes, the increasing density of conductive vias leads to electrical interference and reliability issues, such as stress concentration and defects, which affect device performance and yield, particularly in multi-stack structures.
Innovation Solution
A semiconductor device design incorporating a polymer liner between the sidewall of through substrate vias (TSVs) and the substrate, formed using a pulsed etching process, to alleviate electrical interference and improve hybrid bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between adjacent conductive vias is reduced to increase device density, then device density is improved, but electrical interference increases and device performance decreases
Solution Approach 1:
A polymer liner is introduced as an intermediary material between adjacent through substrate vias (TSVs). This polymer liner acts as a spacer that physically separates the conductive vias, thereby reducing electrical interference while maintaining high device density. The polymer material provides electrical isolation between neighboring vias, enabling closer spacing without performance degradation.
Solution Approach 2:
The polymer liner is formed as a thin film structure between the TSV sidewalls and the substrate. This thin polymer film provides effective electrical isolation and stress relief without occupying excessive space, allowing the device to achieve high density while maintaining proper via spacing to prevent electrical interference.
2Quantity of substance
If smaller dimension TSVs are used to increase device density, then device density is improved, but stress concentration increases and reliability issues occur
Solution Approach 1:
The polymer liner is formed beforehand between the TSV sidewalls and the substrate before final device operation. This pre-formed polymer cushioning layer absorbs and distributes mechanical stress, preventing stress concentration in smaller dimension TSVs. The polymer material acts as a buffer that mitigates stress-related reliability issues while enabling higher device density through smaller via dimensions.
3Reliability
If a polymer liner is formed between TSV sidewall and substrate, then stress concentration is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The polymer liner is applied locally only in the critical regions between TSV sidewalls and the substrate, rather than throughout the entire device structure. This localized application provides stress relief and reliability improvement precisely where needed, while minimizing the overall structural complexity and avoiding unnecessary modifications to other device components.
4Manufacturing precision
If pulsed etching operation is used to form polymer liner, then manufacturing precision is improved, but manufacturing process complexity increases
Solution Approach 1:
A pulsed etching operation is employed to form the polymer liner, where the etching process is applied in periodic pulses rather than continuously. This periodic action allows for precise control of the polymer liner thickness and morphology, achieving high manufacturing precision. The pulsed process enables better material deposition control and reduces defects, though it does increase process complexity compared to continuous etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polymer liner reduces stress concentration and electrical interference, enhancing device performance and yield by improving the reliability of TSVs and hybrid bonding operations.
Implementation Method 1
performing a pulsed etching operation to form a polymer liner in the first recess
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.


