Semiconductor Package Polymer Pattern Crack Control
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Solution Overview
Problem
Current semiconductor package manufacturing methods face challenges in efficiently separating semiconductor chips from substrates without causing dicing failures, particularly due to the propagation of cracks during the stealth dicing process.
Innovation Solution
A method involving the formation of a semiconductor substrate with redistribution layer patterns and a polymer pattern that reveals bonding and edge pad portions, where a dicing line is set in the boundary region to perform a stealth dicing process, separating semiconductor chips while preventing crack propagation through the polymer pattern, and connecting these chips to a package substrate using bonding wires supported by the polymer pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stealth dicing process is performed to separate semiconductor chips from the substrate, then chip separation is achieved, but cracks may propagate causing dicing failures
Solution Approach 1:
The patent applies preliminary action by forming a polymer pattern and setting a dicing line in the boundary region before performing the stealth dicing process. The polymer pattern is prepared in advance to control and prevent crack propagation during the dicing process, thereby resolving the contradiction between achieving chip separation and preventing dicing failures.
2Area of stationary object
If bonding wires are formed close to edge pad portions for compact layout, then space is saved, but electrical connection reliability may be compromised
Solution Approach 1:
The patent uses the polymer pattern as an intermediary element that supports the bonding wires and maintains their spacing from the edge pad portions. The polymer pattern acts as a mediator that enables compact layout while ensuring electrical connection reliability by preventing direct contact between bonding wires and edge pad portions.
Data Source
AI summary
A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.