Polymer Pillar Package Structure for PCB Thermal Mismatch
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Solution Overview
Problem
Conventional semiconductor device packages experience failures due to thermal mismatch between the die and the PCB, leading to issues such as solder ball cracking and cross-talk, which affects the functionality of electronic devices.
Innovation Solution
The use of semiconductor device packages with raised portions, such as pillars, that extend from the die and are coupled with conductive layers to reduce the thermal mismatch by spacing the die apart from the PCB, eliminating the need for solder balls at each bonding pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder balls are used to mount the WLCSP to the PCB, then electrical connections are established, but thermal mismatch causes solder ball failure due to differential expansion and contraction
Solution Approach 1:
The patent introduces an intermediary layer (underfill material or compliant mounting structure) between the die and PCB that acts as a buffer to absorb thermal expansion differences. This intermediary component prevents direct stress transmission from the PCB to the solder joints, thereby reducing solder ball failure caused by thermal mismatch.
Solution Approach 2:
The patent modifies the mounting structure by changing from direct solder ball attachment to a compliant mounting approach using materials with appropriate mechanical properties. The underfill material or compliant layer changes the stress distribution parameters, reducing peak stresses on solder joints during thermal cycling.
2Reliability
If conductive pads are spaced far apart to prevent solder ball cross-talk, then solder ball failures are avoided, but device area increases
Solution Approach 1:
The patent uses an intermediary underfill material or compliant layer that prevents solder ball cross-talk through material isolation rather than spatial separation. This allows conductive pads to be placed closer together while maintaining reliability, as the intermediary material prevents direct contact and electrical cross-contamination between adjacent solder joints.
3Ease of operation
If the die is mounted directly to the PCB, then electrical connections are established, but thermal expansion mismatch causes connection failure
Solution Approach 1:
The patent introduces an underfill material or compliant mounting layer as an intermediary between the die and PCB. This intermediary simplifies the mounting process by providing a forgiving interface that accommodates misalignment and thermal expansion differences, while simultaneously improving connection stability through stress distribution and thermal compliance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the likelihood of defects and malfunctions by minimizing the effects of thermal expansion mismatch, maintaining stable electrical connections and preventing cross-talk, thus enhancing the reliability of electronic devices.
Implementation Method 1
the die has a coefficient of thermal expansion (CTE) that is less than a CTE of the PCB. This difference in the CTEs results in the die and the PCB expanding and contracting by different amounts when exposed to changes in temperature
Data Source
AI summary
The present disclosure is directed to semiconductor packages that include a molding compound having at least one raised portion that extends outward from the package. In some embodiments, the semiconductor packages have a plurality of raised portions, and a plurality of conductive layers are on the plurality of raised portions. The plurality of raised portions and the plurality of conductive layers are utilized to mount the semiconductor packages to an external electronic device (e.g., a printed circuit board (PCB), another semiconductor package, an external electrical connection, etc.). In some embodiments, the semiconductor packages have a single raised portion with a plurality of conductive layers that are on the single raised portion. The single raised portion and the plurality of conductive layers are utilized to mount the semiconductor packages to the external electronic device. The plurality of conductive layers on the plurality of raised portions or the single raised portion may be formed by a laser direct structuring (LDS) process.