Polymer Routing Layer for High Density Cross Link Die Interconnects
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Solution Overview
Problem
Conventional multi-chip modules face limitations in increasing chip-to-chip interconnects due to limited minimum line spacing, leading to higher I2R losses and inductance, particularly in high-density cross-link (HDCL) designs, which hinder efficient power and signal delivery.
Innovation Solution
The use of a polymer layer with thicker, wider conductor traces for lateral routing, potentially replacing the high-speed interconnect portion of HDCL dies, and integrating a redistribution layer (RDL) structure for both DC and AC power delivery, allowing for reduced inductance and improved yield by using a dummy HDCL die for mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional multi-chip modules use standard conductor trace dimensions, then manufacturing is simpler, but I2R losses and inductance increase
Solution Approach 1:
The patent changes the physical parameters of conductor traces by implementing thicker and wider traces in the polymer layer compared to conventional designs. This parameter change directly reduces I2R losses by increasing the cross-sectional area for current flow, thereby lowering resistance and energy loss.
Solution Approach 2:
The patent introduces an additional routing dimension by using the polymer layer as a separate plane for lateral routing. This allows power and signal delivery to occur in a different dimensional plane, separating high-current paths from signal paths and reducing inductance through optimized geometry.
2Productivity
If HDCL dies use standard routing layers, then manufacturing is easier, but interconnect density is limited
Solution Approach 1:
The patent utilizes the polymer layer as an additional routing dimension, enabling lateral routing of power and signals in a separate plane from the traditional metal layers. This dimensional addition significantly increases interconnect density without complicating the manufacturing process, as the polymer layer is applied as a standard encapsulation material.
Solution Approach 2:
The polymer layer serves multiple functions simultaneously: it acts as an encapsulation material for mechanical protection, as a routing layer for power and signal delivery, and as a structural support element. This multi-functionality increases interconnect density without requiring additional dedicated routing structures.
3Power
If thicker, wider conductor traces are used in the polymer layer, then power delivery efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The polymer layer is applied using standard encapsulation processes that automatically form the conductor traces through additive manufacturing or co-curing techniques. The traces are formed as integral parts of the polymer application process, eliminating the need for separate high-precision trace fabrication steps and reducing manufacturing precision requirements.
Solution Approach 2:
The patent merges the power delivery function with the encapsulation function by integrating conductor traces directly into the polymer layer during the encapsulation process. This combination allows thick, wide traces for efficient power delivery to be created using the same manufacturing process that provides mechanical protection, without requiring separate high-precision fabrication steps.
4Reliability
If a dummy HDCL die is used for mechanical support, then yield improves, but device complexity increases
Solution Approach 1:
The patent uses a dummy HDCL die that replicates the mechanical and structural characteristics of functional dies without containing active circuitry. This copy provides the necessary mechanical support and structural integrity for the package while eliminating the complexity and cost of manufacturing and testing fully functional high-density cross-link dies solely for support purposes.
Solution Approach 2:
The dummy HDCL die serves as a sacrificial structural element that provides mechanical support during assembly and operation but contains no valuable functional components. Using a simplified, non-functional die for this purpose reduces overall device complexity and cost compared to using fully functional dies, while still achieving the required mechanical support and yield improvement.
Data Source
AI summary
Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.