Tilted Polymer Sidewalls in Fan-Out Packaging for Dense I/O

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Solution Overview

Problem

As semiconductor dies become smaller and more functional, packaging technologies face challenges in increasing the number of I/O pads in a limited area, leading to issues such as solder bridges and limited solder ball packing density.

Innovation Solution

The development of fan-out packages, where the I/O pads on a die are redistributed to a larger area, allowing for increased I/O pad density, and the use of tilted sidewalls in the encapsulating material to facilitate smoother encapsulation and reduce stress on the die.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fan-in packaging is used with smaller dies, then throughput and cost are improved, but the number of I/O pads is limited due to area constraints and pitch limitations

Engineering Contradiction:
ImprovethroughputVSAvoidnumber of I/O pads
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent transitions from fan-in packaging (I/O pads confined to die surface area) to fan-out packaging (I/O pads redistributed to a larger area beyond the die boundaries). This dimensional expansion allows the same die to support significantly more I/O pads by utilizing the substrate area rather than being constrained to the die footprint, directly resolving the contradiction between maintaining high throughput and increasing I/O pad quantity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If I/O pad pitch is decreased to increase pad density, then more pads can be packed, but solder bridges occur

Engineering Contradiction:
Improvenumber of I/O padsVSAvoidsolder bridge prevention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

By redistributing I/O pads to a larger area through fan-out packaging, the patent increases the effective spacing between pads without requiring smaller pitch on the die itself. This maintains solder joint reliability while achieving higher overall pad density, as pads are spread across a larger footprint rather than being compressed into a smaller area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If vertical sidewalls are used in encapsulating material, then packaging structure is simple, but stress on die during encapsulation is high

Engineering Contradiction:
Improveencapsulation structureVSAvoidstress on die
Core Design Contradiction:
Device complexityVSStress or pressure

Solution Approach 1:

The patent replaces vertical sidewalls with tilted sidewalls in the encapsulating material structure. This geometric modification distributes the encapsulation stress more evenly across the die surface, reducing peak stress concentrations that would occur with abrupt vertical transitions. The tilted angle provides a gradual transition zone that mitigates mechanical stress while maintaining structural integrity.

Inventive Principle:
Principle #14Spheroidality (Curvature)

4Quantity of substance

If fan-out packaging is used to increase I/O pad area, then I/O pad density is improved, but device complexity increases

Engineering Contradiction:
ImproveI/O pad densityVSAvoidpackaging structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the packaging structure into distinct functional layers and regions: the die itself, the encapsulating material with tilted sidewalls, and the substrate area for I/O redistribution. This segmentation allows each component to be optimized independently - the die maintains its original compact design while the surrounding encapsulation and substrate provide the expanded I/O interface, thereby achieving high I/O density without proportionally increasing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12334406B2Package with tilted interface between device die and encapsulating material
Publication Date: 2025.06.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12334406B2 patent drawing
  • US12334406B2 patent drawing
  • US12334406B2 patent drawing

AI summary

A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.