Self-Aligned Polymer Spacers for Sub-40nm Via Etching
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Solution Overview
Problem
Current integrated circuit manufacturing techniques are costly and limited by resolution capabilities, requiring multiple photomasks and iterative steps that increase production costs and risk of misalignment, making it difficult to achieve small-scale geometries and efficient structure creation.
Innovation Solution
A method involving the formation of a polymer layer on a dielectric layer to create spacers for etching, allowing for the creation of smaller features and structures without the need for additional photomasks, using in-situ polymer deposition and controlled etching to form structures like vias and trenches with improved resolution and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks are used to create small-scale structures, then manufacturing precision is improved, but device complexity and production cost increase
Solution Approach 1:
The patent employs self-aligned spacer formation where the spacer structure automatically defines the via location and dimensions. The spacer is formed conformally on the trench sidewalls, and its thickness directly determines the via geometry. This self-aligned approach eliminates the need for separate photomasks to define via positions, as the spacer itself serves as the alignment reference for subsequent etching steps.
Solution Approach 2:
The patent performs preliminary trench formation and spacer deposition before final via etching. The spacer is formed in advance on the trench sidewalls with controlled thickness, and this pre-formed spacer then guides the via etch process. This preliminary action allows the via dimensions to be precisely controlled by the spacer thickness rather than requiring a separate photomask definition step.
2Manufacturing precision
If multiple photomasks are used for iterative manufacturing steps, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The self-aligned spacer formation process uses the trench structure itself as the reference for spacer placement, eliminating the need for wafer removal and remasking between steps. The spacer automatically forms at the correct location with proper alignment, allowing continuous processing and improving throughput while maintaining precision.
Solution Approach 2:
The patent combines multiple functions into a single spacer formation process: the spacer simultaneously defines the via location, controls via dimensions, and serves as the etch mask. This merging of multiple functions that would traditionally require separate photomask steps into a single self-aligned process reduces the number of iterative steps and improves productivity.
3Ease of manufacture
If conventional etching techniques are used, then ease of manufacture is maintained, but manufacturing precision deteriorates due to resolution limits
Solution Approach 1:
The patent introduces a polymer spacer as an intermediary element between the trench structure and the final via. The spacer is deposited conformally on the trench sidewalls and serves as a mediator that defines the via geometry. This intermediary allows precise via dimension control through spacer thickness control rather than relying solely on etch resolution, achieving better precision while maintaining process simplicity.
Solution Approach 2:
The patent controls via dimensions by changing the spacer deposition parameters (such as deposition time and thickness) rather than changing the etch parameters or photomask features. By controlling the spacer thickness parameter, precise via dimensions can be achieved with conventional etching equipment, improving manufacturing precision without complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of smaller geometries and features, such as vias with widths less than 40 nm, reduces production costs by eliminating the need for additional photomasks, and improves alignment accuracy, achieving more efficient and cost-effective integrated circuit manufacturing.
Implementation Method 1
A method involving the formation of a polymer layer on a dielectric layer to create spacers for etching, allowing for the creation of smaller features and structures
Implementation Method 2
The process of removing material generally includes an etching process. It is through the etching process that material in regions defined by the pattern is removed to form various structures
Data Source
AI summary
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.