Polymer Substrate for RF Power Switches Reducing Nonlinearities
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Solution Overview
Problem
Conventional RFCMOS SOI technologies face nonlinearities due to high resistivity silicon handle regions interfaced with buried oxide dielectric regions, leading to complex and costly process solutions that are not effectively mitigated, limiting the performance of RF switches in 3G and 4G wireless applications.
Innovation Solution
A printed circuit module with a polymer substrate replaces the silicon wafer handle, providing a low-resistivity layer with high thermal conductivity and electrical resistivity, eliminating the need for high resistivity silicon substrates and simplifying the manufacturing process, while maintaining ideal linear characteristics and enabling higher RF power levels and frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistivity silicon handle layer is used to maintain isolation between stacked FETs, then electrical isolation is improved, but RF nonlinearities increase due to the silicon/oxide interface
Solution Approach 1:
The patent changes the material parameter of the handle layer from high resistivity silicon to a material with low resistivity (such as silicon with resistivity less than 100 Ohm-cm). This parameter change eliminates the RF nonlinearities caused by the silicon/oxide interface while maintaining electrical isolation through alternative design approaches such as increased BOX thickness or optimized FET stacking configurations.
Solution Approach 2:
The patent replaces the expensive high resistivity silicon handle layer with a lower cost, standard resistivity silicon substrate. The high resistivity handle layer is essentially discarded and replaced with a simpler, more readily available material that achieves the same functional goals without the harmful interface effects.
2Reliability
If complex process steps and heating treatments are applied to mitigate nonlinearities, then RF linearity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and removes the source of nonlinearities (the high resistivity silicon/oxide interface) from the device structure. By eliminating this problematic interface through the use of low resistivity silicon, the complex mitigation processes (trap rich interface creation, harmonic suppression treatments) become unnecessary, significantly simplifying the manufacturing process.
Solution Approach 2:
Instead of applying complex treatments to fix the nonlinearities caused by high resistivity silicon, the patent inverts the approach by using low resistivity silicon from the outset. This fundamental reversal of the material selection strategy eliminates the need for subsequent corrective process steps.
3Reliability
If high resistivity silicon substrates are used for RFCMOS SOI technology, then FET stacking isolation is maintained, but processing cost and complexity increase
Solution Approach 1:
The patent replaces expensive high resistivity silicon substrates with standard resistivity silicon that is widely available and much cheaper to manufacture. The high resistivity material is discarded in favor of economical standard silicon, achieving the same isolation performance through simpler, lower-cost processes.
Solution Approach 2:
The patent changes the resistivity parameter of the silicon substrate from high (1000-5000 Ohm-cm) to low (less than 100 Ohm-cm), fundamentally altering the material properties to reduce cost while maintaining functionality through alternative isolation mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polymer substrate solution reduces RF nonlinear effects, allows for more efficient stacking of NFET transistors, and extends the operational frequency of RF power switches beyond traditional limits, achieving near-ideal voltage stacking and higher RF power levels with simpler and cost-effective processing.
Implementation Method 1
the outer protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK)
Implementation Method 2
an electrical resistivity of greater than 10³ Ohm-cm
Data Source
AI summary
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.