Polymer Substrate Integrated Circuit Package for RF Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional RFCMOS SOI technologies face limitations due to high resistivity silicon wafer handles, leading to nonlinearities and increased complexity and cost, which are not effectively mitigated by existing solutions such as trap rich silicon/oxide interfaces and harmonic suppression processes.
Innovation Solution
The use of a polymer substrate replaces the silicon wafer handle, allowing for a simpler process flow, reduced cost, and elimination of nonlinear effects, enabling higher RF power levels and frequency operation by providing ideal voltage stacking and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high resistivity silicon wafer handles are used, then isolation between stacked low voltage FETs is maintained, but nonlinearities and RF intermodulation occur
Solution Approach 1:
The patent changes the material parameter from high resistivity silicon (1000-5000 Ohm-cm) to polymer substrate with resistivity greater than 10^12 Ohm-cm. This parameter change eliminates the interface between silicon handle and BOX dielectric region, thereby removing the source of nonlinearities and RF intermodulation while maintaining electrical isolation between stacked FETs.
Solution Approach 2:
The patent replaces expensive high resistivity silicon substrates with cheaper polymer substrates. The polymer substrate serves the same electrical isolation function without the harmful interface effects, reducing both cost and performance issues associated with silicon handle wafers.
2Object-generated harmful factors
If trap rich silicon/oxide interface or harmonic suppression processes are used, then nonlinearities are mitigated, but process complexity and cost increase
Solution Approach 1:
The patent extracts and removes the problematic silicon handle wafer from the device structure entirely. By replacing it with a polymer substrate, the need for complex harmonic suppression processes and trap rich interface engineering is eliminated, as the source of nonlinearities (the silicon/oxide interface) is removed.
Solution Approach 2:
The patent uses a simple polymer substrate replacement that eliminates the need for complex post-fabrication processes. The polymer material inherently provides the desired electrical properties without requiring additional heating treatments, process steps, or specialized interface engineering.
3Reliability
If high resistivity silicon substrates are used, then RF device linearity is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive high resistivity silicon substrates with inexpensive polymer substrates that provide equal or superior electrical isolation. The polymer material achieves the same RF performance benefits without the high material cost and complex manufacturing requirements of high resistivity silicon.
Solution Approach 2:
The patent changes the substrate material parameter from silicon to polymer, achieving resistivity greater than 10^12 Ohm-cm. This parameter change provides excellent electrical isolation for RF applications at lower cost and with simpler manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in RF switch devices with linear characteristics close to ideal, capable of operating at higher RF power levels and frequencies, and eliminates the need for complex and costly high resistivity silicon substrates, facilitating migration to 300 mm substrates for improved die costs and efficiency.
Implementation Method 1
The second polymer layer may be provided to have high thermal conductivity and electromagnetic isolation properties thereby providing advantageous package characteristics by allowing high thermal conduction
Implementation Method 2
The second polymer layer may be provided to have high thermal conductivity and electromagnetic isolation properties thereby providing advantageous package characteristics by allowing high thermal conduction yet protecting the semiconductor devices in the FEOL region from electromagnetic radiation
Data Source
AI summary
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.