Integrated Polymer Trench Capacitor for Interposer Space Optimization
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Solution Overview
Problem
Conventional decoupling capacitors on interposers occupy valuable space, have low capacitance values, and limit die placement due to their large size and rectangular shape, which is inefficient for 2.5D applications and beyond, especially in 65 nm designs using through-silicon vias (TSV).
Innovation Solution
An integrated polymer trench capacitor is formed on the interposer surface by creating trenches in a polymer block, conformally depositing metal and dielectric layers, and forming connection pads, allowing for high-capacitance and low-profile capacitors that can be easily integrated into existing BEOL/RDL processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If surface-mounted capacitors are used on the interposer surface, then capacitance values can be achieved, but they take up valuable space on the interposer surface that could be used for die placement
Solution Approach 1:
The capacitor structure transitions from a surface-mounted 2D configuration to a trench-based 3D configuration. By etching trenches into the interposer substrate and forming capacitor electrodes within these trenches, the design utilizes the vertical dimension (depth) to increase capacitance density. This allows the capacitor to occupy less surface area while maintaining or increasing the capacitance value, as the capacitance is now distributed throughout the volume of the trench rather than just on the surface.
2Quantity of substance
If surface-mounted capacitors are used, then capacitance can be provided, but they must be square/rectangle shaped which limits the placement of dies on the interposer
Solution Approach 1:
The capacitor structure is segmented into multiple components: the trench structure, the dielectric material filling the trench, and the electrode patterns. The electrode patterns can be designed in various configurations (e.g., interdigitated fingers, meandering patterns) that can adapt to different available spaces on the interposer. This segmentation allows the capacitor to be customized in shape and size to fit around dies or in unused areas, providing flexibility in die placement while maintaining the required capacitance value.
3Area of stationary object
If integrated capacitors are formed in the interposer routing, then space is utilized, but they take up valuable space that could otherwise be used for signal routing in BEOL/RDL
Solution Approach 1:
The capacitor structure utilizes the vertical dimension by forming trenches that extend into the substrate depth. This 3D configuration allows the capacitor to occupy minimal surface area while providing sufficient capacitance. The BEOL/RDL signal routing layers can be positioned above or around the trench structures, maintaining full routing capacity without significant interference from the capacitor formation.
4Quantity of substance
If conventional decoupling capacitors are used, then decoupling function is provided, but they have low capacitance values relative to the space occupied
Solution Approach 1:
The capacitor structure employs a nested configuration where the dielectric material is positioned within the trench, and the electrode patterns are arranged around and within the dielectric. This nested arrangement maximizes the use of available space within the trench volume, increasing the effective capacitance density. The multi-layer electrode structure nested within the trench provides high capacitance in a compact footprint, improving the capacitance-to-area ratio compared to conventional surface-mounted capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a high-capacitance, low-profile capacitor that efficiently uses interposer surface space, enabling better die placement and increased capacitance density, which is suitable for 2.5D applications and beyond, including 65 nm designs with TSVs.
Implementation Method 1
patterning and etching the polymer block to form one or more trenches
Implementation Method 2
conformally forming a first metal layer in the one or more trenches, upper and side surfaces of the polymer block
Implementation Method 3
forming a capacitor on an upper surface of the polymer block and in the one or more trenches
Data Source
AI summary
A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.