Polymeric Layer for Semiconductor Solder Stress Relief

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Solution Overview

Problem

Conventional semiconductor die mounting techniques using lead-free solders face mechanical stress issues due to the relative positioning of polyimide and under bump metallization layers, leading to potential solder ball cracks and electrical failures.

Innovation Solution

A method where a polymeric layer is positioned between the conductor structure and the solder structure on the semiconductor die, allowing for stress reduction and improved mechanical integrity by acting as a compliant interface between the solder and the metallization layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If lead-free solder is used instead of lead-based solder, then environmental compliance and solder strength are improved, but ductility decreases and mechanical stress resistance deteriorates

Engineering Contradiction:
Improvesolder reliabilityVSAvoidsolder ductility
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent introduces a polymeric layer as an intermediary between the under bump metallization layer and the solder ball. This polymeric layer acts as a stress-absorbing intermediary that protects the brittle lead-free solder from mechanical stresses caused by thermal expansion mismatches, thereby maintaining solder reliability without sacrificing ductility.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies a polymeric layer beforehand to cushion and absorb mechanical stresses before they reach the solder ball. This pre-positioned protective layer prevents stress concentration at the solder-metallization interface, protecting the lead-free solder from cracking during thermal cycling and mechanical loading.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If polyimide layer is positioned between under bump metallization layer and passivation layer, then electrical insulation is improved, but stress reduction capability deteriorates

Engineering Contradiction:
Improveelectrical insulationVSAvoidmechanical stress on solder
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The patent inverts the conventional layer arrangement by positioning the polymeric layer between the under bump metallization layer and the solder ball, rather than between the metallization layer and the passivation layer. This inverted positioning allows the polymeric layer to directly cushion the solder ball from mechanical stresses while the polyimide layer maintains its electrical insulation function elsewhere in the structure.

Inventive Principle:
Principle #13The other way round (Inversion)

3Manufacturing precision

If stencil paste process is used for solder deposition, then manufacturing precision is improved, but stress distribution deteriorates

Engineering Contradiction:
Improvesolder placement precisionVSAvoidstress concentration in solder
Core Design Contradiction:
Manufacturing precisionVSStress or pressure

Solution Approach 1:

The patent changes the physical and chemical parameters of the interface between the solder and the substrate by introducing a polymeric layer. This layer modifies the stress distribution parameters at the solder-metallization interface, creating a more gradual stress gradient that prevents stress concentration even when using precision stencil paste deposition methods.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces mechanical stresses on solder balls, enhancing their reliability and preventing cracks, thereby improving the reliability of semiconductor devices by providing a compliant interface that mitigates thermal expansion mismatches.

Implementation Method 1

The significance of this arrangement will be explained in further detail below. After the under bump metallization layer is formed... the polyimide layer is positioned between the under bump metal layer and the passivation layer. The significance of this arrangement will be explained in further detail below... the stress reducing abilities of the polyimide layer are not available to the solder balls

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Implementation Method 2

The stencil is removed and a thermal process is performed to reflow the solder structures. The solder structures solidify into ball-like structures.

Methodology Applied
Scientific EffectReflow: Melting

Implementation Method 3

Electrical conductivity between the die and the underlying substrate or board is established through a variety of conventional mechanisms. In a so-called flip-chip configuration, the active circuitry side of the die is provided with a plurality of conductor balls or bumps that are designed to establish a metallurgical bond with a corresponding plurality of conductor pads positioned on the substrate or circuit board.

Methodology Applied
Scientific EffectMetallurgical bond: Diffusion Welding

Implementation Method 4

Lead-free solder materials tend to have relatively lower ductility than lead-based solders. This increased stiffness can lead to significant stresses in the solder balls, particularly where operating temperatures are high or where there is a significant mismatch between the coefficients of thermal expansion between the semiconductor die and the substrate upon which it is mounted.

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8294266B2Conductor bump method and apparatus
Publication Date: 2012.10.23 ADVANCED MICRO DEVICES INC
  • US8294266B2 patent drawing
  • US8294266B2 patent drawing
  • US8294266B2 patent drawing

AI summary

Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.