Polymorphic On-Chip Network Configuration for Custom Silicon Chips
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Solution Overview
Problem
Current technologies face challenges in achieving optimal performance across varying traffic patterns and applications due to the inability to configure on-chip networks post-fabrication, leading to suboptimal performance in both fixed and programmable devices.
Innovation Solution
A polymorphic network architecture that allows for the dynamic configuration of network topology, link bandwidth, and buffering after fabrication, enabling customization of the interconnection scheme before runtime to match specific application requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed ASIC design is used, then manufacturing cost is reduced and performance is improved, but adaptability to different applications and traffic patterns deteriorates
Solution Approach 1:
The patent implements dynamic reconfigurability in the network interconnect layer, allowing the system to transition from a fixed ASIC architecture to a dynamically adaptable architecture. The network topology, routing algorithms, and bandwidth allocation can be reconfigured at runtime to match different application requirements and traffic patterns, while the functional blocks remain as fixed ASIC components. This resolves the contradiction by introducing dynamics only where needed (interconnect) rather than throughout the entire system.
Solution Approach 2:
The system is segmented into two distinct layers: fixed functional blocks (ASIC components) and a reconfigurable network interconnect layer. This segmentation allows each layer to be optimized independently - the functional blocks maintain fixed, high-performance ASIC characteristics while the network layer provides adaptability through reconfiguration. This segmentation resolves the contradiction by isolating the adaptability requirement to a specific subsystem rather than requiring full-system reconfigurability.
2Adaptability or versatility
If a reconfigurable network is implemented, then adaptability to different applications is improved, but device complexity and design costs increase
Solution Approach 1:
The reconfigurable network is segmented into modular components including configurable routers, switches, and topology elements that can be independently controlled. This modular segmentation reduces overall device complexity by allowing each component to be designed and verified separately, then integrated through standardized interfaces. The segmentation enables manageable complexity while maintaining high adaptability.
Solution Approach 2:
The network interconnect is designed as a universal platform that can serve multiple different applications and traffic patterns through reconfiguration. Rather than designing separate specialized networks for each application, a single multi-functional network infrastructure handles diverse workloads by dynamically adjusting its topology and routing behavior. This universality reduces device complexity compared to having multiple specialized systems.
3Manufacturing precision
If network configuration is fixed at fabrication, then manufacturing precision is improved, but performance optimization for specific applications deteriorates
Solution Approach 1:
The network configuration transitions from a static fixed state at fabrication to a dynamic reconfigurable state at runtime. The manufacturing process fabricates the physical network infrastructure with precise, fixed connections, while the logical configuration (topology, routing, bandwidth allocation) remains dynamic and can be optimized for specific applications before execution. This separation of physical fixedness from logical flexibility resolves the contradiction between manufacturing precision and performance optimization.
Solution Approach 2:
The system performs preliminary network configuration and optimization actions before runtime execution. The network can be pre-configured with optimal topology and routing parameters tailored to specific applications prior to actual operation, allowing performance optimization without requiring changes to the physical manufacturing process. This preliminary configuration action enables application-specific performance tuning while maintaining manufacturing simplicity.
4Quantity of substance
If ASIC production is used, then unit cost and power consumption are reduced, but design and verification costs increase
Solution Approach 1:
The design and verification workload is segmented between fixed functional blocks and the reconfigurable network interconnect. The functional blocks can be designed and verified once using standard ASIC methodologies, while the network layer uses more automated and flexible verification approaches suitable for reconfigurable systems. This segmentation reduces overall design and verification costs compared to fully custom ASIC design by allowing reuse of verified functional block designs.
Solution Approach 2:
The patent employs standardized, reusable functional block designs that can be copied and instantiated multiple times within the ASIC fabric. Rather than designing unique custom logic for each application, proven functional blocks are replicated and interconnected through the reconfigurable network. This copying approach reduces design and verification costs by eliminating redundant design efforts while maintaining ASIC-level unit cost and power efficiency.
Data Source
AI summary
A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.