Polynomial Block Encoding for Low-Complexity LDPC Error Correction
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Solution Overview
Problem
Conventional low-density parity-check (LDPC) error correction encoding apparatuses are large in size and complex, requiring significant calculation and storage, making them unsuitable for high-code-rate systems like satellite communications and mobile telecommunications, and they rely on experimental methods for error-rate characteristic evaluation, which is time-consuming, especially in low error probability areas.
Innovation Solution
A simplified error correction encoding apparatus using (m−1) polynomial multiplying units and a polynomial dividing unit to divide information bit strings into blocks, performing polynomial multiplication and division to generate redundant bits, allowing for iterative decoding and mathematical evaluation of error-floor characteristics without computer simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC encoding apparatus uses matrix multiplication by generator matrix, then error correction capability is achieved, but the number of exclusive-OR operations required is proportional to the square of the code length, making the apparatus large and complex
Solution Approach 1:
The information bit sequence is divided into multiple blocks, and the encoding is performed block by block. This segmentation allows the use of a simplified encoding structure for each block rather than processing the entire sequence at once, reducing the complexity of the encoding apparatus while maintaining error correction capability.
Solution Approach 2:
The patent changes the encoding approach from traditional matrix multiplication to a method based on dividing the information sequence into blocks and processing each block independently. This parameter change in the encoding methodology reduces the number of exclusive-OR operations from being proportional to the square of the code length to a more manageable count, simplifying the apparatus structure.
2Ease of manufacture
If conventional LDPC encoding uses transformed check matrix with elementary matrix transformations, then encoding can be realized, but the apparatus requires significant storage units to hold the matrix and perform operations
Solution Approach 1:
By segmenting the information bit sequence into blocks and processing each block independently, the patent reduces the storage requirements compared to holding the entire transformed check matrix in memory. Each block can be processed with reduced matrix storage, thereby reducing the overall quantity of storage units needed while still enabling encoding implementation.
Solution Approach 2:
The patent extracts and processes only the necessary portions of the encoding operation at each step rather than requiring the complete transformed check matrix to be stored and accessed. This extraction approach reduces the storage unit requirement while maintaining the ability to perform encoding operations.
3Measurement precision
If conventional LDPC evaluation uses experimental methods with computer simulations, then error-rate characteristics can be evaluated, but it is time-consuming particularly in low error probability areas
Solution Approach 1:
The patent performs preliminary analysis by dividing the information sequence into blocks and pre-processing each block independently. This preliminary action allows for more efficient subsequent evaluation of error-rate characteristics, reducing the time required for experimental methods and computer simulations, particularly in low error probability areas where extensive simulation would otherwise be needed.
Data Source
AI summary
An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n−1)-th-order polynomial multiplying units (12-1 to 12-(m−1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m−1) blocks having a length n and a single block having a length (n−r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length. An r-th-order polynomial dividing unit 2 receives an addition of the outputs from the respective (n−1)-th-order polynomial multiplying units (12-1 to 12-(m−1)) and also receives a block having the length (n−r), and outputs a redundant bit series having a length r.