Polynomial Circuitry Bit-Slice Summation for FPGA LUT Efficiency
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Solution Overview
Problem
Evaluating shifted polynomials in programmable devices like FPGAs is inefficient due to inefficient packing of partial products into look-up tables (LUTs), leading to increased resource count and reduced performance, especially in applications requiring high-speed operations like Chien searches for BCH and Reed-Solomon codes.
Innovation Solution
The method involves summing partial products across all multipliers in a bit-slice-by-bit-slice order, shifting and then summing the bit-slice sums, which allows efficient packing into LUTs and supports pipelining, reducing the need for additional programmable logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If partial products are summed by adding multiple shifted partial products for each term and then adding together all sums, then polynomial evaluation can be performed, but the addition operations do not pack efficiently into LUTs resulting in increased resource count and reduced performance
Solution Approach 1:
The patent segments the addition operations into bit-slice level operations. Instead of adding all partial products at once, it processes them bit-by-bit across all terms, creating bit-slice sums that can be efficiently packed into LUTs. This segmentation enables efficient resource utilization while maintaining high evaluation speed.
Solution Approach 2:
The patent introduces a bit-slice dimension to the addition operations. By organizing additions across bit positions rather than by term, it transforms the operation structure to match LUT packing capabilities. This dimensional reorganization allows efficient parallel processing and reduces resource requirements.
2Speed
If traditional addition methods are used to sum partial products, then polynomial evaluation is achieved, but inefficient packing into LUTs increases the logic path length and reduces operating speed
Solution Approach 1:
The patent segments the computation into bit-slice operations that can be performed in parallel. By processing bits at the same position across all terms simultaneously, it creates short logic paths that fit efficiently within LUTs, enabling high-speed operation without increasing logic path length.
Solution Approach 2:
The patent performs preliminary bit-slice summations before the final addition. By pre-computing bit-slice sums for each position, it prepares data in an optimized format that reduces subsequent operation complexity and shortens the overall logic path, enabling faster operation.
Data Source
AI summary
Polynomial circuitry includes a respective partial product generator for each bit position of each term of a plurality of terms of a polynomial to be evaluated. A respective plurality of adders for each bit position adds partial products of a respective bit position across all of the plurality of terms to provide a respective bit-slice sum. Resulting bit-slice sums are offset from one another according to their respective bit positions. A final adder adds together the respective offset bit-slice sums to provide a result.