Polynomial Circuitry Using Fixed-Point Arithmetic for Resource Reduction

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Solution Overview

Problem

Computing floating-point polynomials in integrated circuit devices requires substantial resources and latency, especially when using double-precision arithmetic, which is inefficient for applications with small input ranges.

Innovation Solution

Implementing floating-point polynomial calculations using fixed-point resources by denormalizing coefficients and performing calculations as fixed-point operations, reducing the number of required resources and datapath length, and utilizing coefficient tables with shifted values based on exponents for efficient polynomial circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If double-precision floating-point arithmetic is used for polynomial calculations, then calculation precision is improved, but resource consumption increases substantially

Engineering Contradiction:
Improvecalculation precisionVSAvoidresource consumption
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter representation from double-precision floating-point to fixed-point arithmetic. By representing polynomial coefficients and input values in fixed-point format with appropriate bit widths, the system achieves sufficient precision for small input ranges while dramatically reducing the number of required adaptive look-up tables and multipliers in PLD hardware

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent pre-calculates and stores polynomial coefficients in a lookup table during device configuration or initialization. These pre-computed coefficients are loaded into the PLD's memory resources, eliminating the need for complex real-time floating-point coefficient storage and reducing runtime computational complexity

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If double-precision floating-point arithmetic is used for polynomial calculations, then calculation precision is improved, but datapath length increases and latency increases

Engineering Contradiction:
Improvecalculation precisionVSAvoidlatency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent transitions from floating-point to fixed-point arithmetic, which uses simpler hardware circuits with shorter propagation delays. Fixed-point addition and multiplication operations complete in fewer clock cycles compared to floating-point operations, directly reducing calculation latency while maintaining adequate precision for the application's small input range

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If double-precision floating-point arithmetic is used for polynomial calculations, then calculation precision is improved, but the number of adaptive look-up tables and multipliers increases

Engineering Contradiction:
Improvecalculation precisionVSAvoidnumber of adaptive look-up tables and multipliers
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent changes the arithmetic parameter from double-precision floating-point to fixed-point representation. This parameter change allows the same polynomial calculation to be performed with significantly fewer hardware resources—specifically, fewer adaptive look-up tables and multipliers in the PLD—because fixed-point operations require smaller word widths and simpler control logic

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs pre-computation of polynomial coefficients and stores them in a lookup table. This preliminary action allows the runtime calculation to simply retrieve pre-computed values and perform simple fixed-point arithmetic, eliminating the need for numerous multipliers that would be required for real-time floating-point polynomial evaluation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8949298B1Computing floating-point polynomials in an integrated circuit device
Publication Date: 2015.02.03 ALTERA CORP
  • US8949298B1 patent drawing
  • US8949298B1 patent drawing
  • US8949298B1 patent drawing

AI summary

Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, where the input variable has a mantissa and an exponent, and the circuitry has a number of bits of precision, includes multiplier circuitry that calculates a common power of the input variable factored out of terms of the polynomial having powers of the variable greater than 1. The polynomial circuitry further includes, for each respective remaining term of the polynomial that contributes to the number of bits of precision: (1) a coefficient memory loaded with a plurality of instances of a coefficient for the respective term, each instance being shifted by a different number of bits, (2) address circuitry for selecting one of the instances of the coefficient based on the exponent, and (3) circuitry for combining the selected instance of the coefficient with a corresponding power of the input variable to compute the respective term.