Floating-Point Polynomial Circuitry Using Fixed-Point Coefficients
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Solution Overview
Problem
Computing floating-point polynomials in integrated circuit devices requires substantial resources, especially for applications using double-precision or quadruple-precision arithmetic, which can be inefficient and resource-intensive.
Innovation Solution
Implementing floating-point polynomial calculations using fixed-point resources by performing denormalization operations on coefficients and conducting the remainder of the calculation as fixed-point operations, reducing the need for arithmetic and logic resources and minimizing datapath length and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If double-precision floating-point arithmetic is used for polynomial calculations, then calculation precision is improved, but resource consumption increases substantially
Solution Approach 1:
The patent changes the parameter representation from floating-point to fixed-point format. By representing polynomial coefficients in fixed-point format with appropriate fractional positions, the system achieves double-precision calculation accuracy while using significantly fewer hardware resources (ALUTs and multipliers) compared to floating-point implementation.
Solution Approach 2:
The patent segments the polynomial calculation into separate coefficient storage and combination operations. Coefficients are stored in fixed-point format in memory, and the calculation process combines these segmented coefficient values with input values through structured addition and multiplication operations, reducing the need for complex floating-point arithmetic units.
2Measurement precision
If quadruple-precision floating-point arithmetic is used for polynomial calculations, then calculation precision is improved, but resource consumption and device area increase
Solution Approach 1:
The patent applies fixed-point representation to polynomial coefficients, which can represent quadruple-precision values using appropriate fractional bit positions. This approach achieves the required precision without needing specialized quadruple-precision floating-point arithmetic units, thereby reducing device area while maintaining calculation accuracy.
3Measurement precision
If floating-point polynomial calculations are implemented using standard arithmetic resources, then calculation accuracy is maintained, but datapath length and latency increase
Solution Approach 1:
By changing from floating-point to fixed-point parameter representation, the patent enables the use of simpler, faster fixed-point arithmetic operations. This reduces the complexity of arithmetic logic units and shortens datapath length, thereby reducing calculation latency while maintaining sufficient accuracy for the application.
Data Source
AI summary
Polynomial circuitry for calculating a polynomial having terms including powers of an input variable, where the input variable is represented by a mantissa and an exponent, includes at least one respective coefficient table for each respective term, each respective coefficient table being loaded with a plurality of respective instances of a coefficient for said respective term, each respective instance being shifted by a different number of bits. The circuitry also includes decoder circuitry for selecting one of the respective instances of the coefficient for each respective term based on the exponent and on a range, from among a plurality of ranges, of values into which that input variable falls.