Polynomial Coefficient Generator With Parallel Rejection Sampling

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Solution Overview

Problem

Rejection sampling of polynomial coefficients in lattice-based cryptosystems is inefficient due to time delays and inefficiencies in generating random polynomials, which can be broken by quantum computers using Shor's algorithm.

Innovation Solution

A polynomial coefficient generator system that includes a random number generator, a buffer, a rejection sampler, a valid coefficient queue, and a polynomial multiplier, which operates in parallel to efficiently generate and validate polynomial coefficients using a Keccak random number generator and a PISO buffer to balance throughput and reduce memory access conflicts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If rejection sampling is used to generate random polynomial coefficients, then the coefficients satisfy certain conditions, but time delays and inefficiencies occur in polynomial generation

Engineering Contradiction:
Improvecoefficient validityVSAvoidpolynomial generation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system pre-generates and stores n+1 sets of p bits in a buffer before they are needed for polynomial multiplication. This preliminary action ensures that when coefficients are needed, valid sets are already available, eliminating time delays during critical operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The random bit string is divided into multiple sets of p bits, and the rejection sampling process is segmented to process n+1 sets simultaneously. This segmentation allows parallel validation of multiple coefficient candidates, reducing overall generation time while maintaining validity requirements.

Inventive Principle:
Principle #1Segmentation

2Productivity

If parallel processing is used to sample n+1 sets of p bits, then productivity increases, but device complexity increases

Engineering Contradiction:
Improvecoefficient generation rateVSAvoidsampling system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The parallel sampling system is segmented into independent rejection sampler units, each handling a specific set of p bits. This modular segmentation allows the system to achieve high productivity through parallel processing while managing complexity by replicating proven, validated sampling modules rather than designing a monolithic complex system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A queue mechanism serves as an intermediary between the parallel rejection samplers and the polynomial multiplier. This intermediary buffers the n+1 sets of p bits, coordinating their flow and ensuring proper timing without requiring complex direct synchronization between all sampling units, thus simplifying the overall system architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250328599A1Rejection Sampling For Polynomial Coefficient Generator
Publication Date: 2025.10.23 MICROSOFT TECHNOLOGY LICENSING LLC
  • US20250328599A1 patent drawing
  • US20250328599A1 patent drawing
  • US20250328599A1 patent drawing

AI summary

A polynomial coefficient generator includes a random number generator to generate a random bit string. A buffer is coupled to receive bits of the random bit string and a rejection sampler is coupled to the buffer to receive n+1 sets of p bits of buffered bits of the random bit string, where n is an integer having a value of at least four, and sample each set of n bits in parallel to identify valid sets of p bits A valid coefficient queue is coupled to receive the valid sets of p bits, and a polynomial multiplier is coupled to receive the valid sets of p bits from the valid coefficient queue. A method uses the generator to generate valid coefficients.