Polynomial Divide Instruction for Flexible Binary Field Processing
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Solution Overview
Problem
Existing data processing systems provide limited support for general polynomial operations beyond Reed Solomon coding, and specialized hardware for signal scrambling and transmission codes is inflexible and resource-intensive.
Innovation Solution
A programmable data processing apparatus with a polynomial divide instruction that generates quotient and remainder polynomials, allowing for efficient polynomial division over a field of two elements, and optionally includes a polynomial multiply instruction for enhanced functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If specialized hardware is provided for signal scrambling or generating transmission codes, then calculation speed is improved, but circuit resource consumption increases and flexibility decreases
Solution Approach 1:
The patent implements a universal polynomial processing instruction set that can perform multiple polynomial operations (multiplication, division, remainder calculation) using the same hardware resources. The processor can handle different polynomial degrees and coefficients through software configuration rather than requiring dedicated hardware for each function, thereby achieving both high-speed calculation and flexibility.
Solution Approach 2:
The patent uses dynamic configuration of polynomial parameters through software instructions. The degree of polynomials, coefficients, and operation types can be changed at runtime by loading different values into registers and executing appropriate instructions, allowing the same hardware to adapt to different application requirements without physical reconfiguration.
2Speed
If specialized hardware is provided for signal scrambling or generating transmission codes, then calculation speed is improved, but circuit resource consumption increases
Solution Approach 1:
The patent employs a multi-functional processor core that can execute polynomial operations alongside other general-purpose computing tasks. By sharing ALU, registers, and control logic across multiple functions, the design achieves high-speed polynomial processing without requiring separate dedicated hardware circuits, thereby reducing overall device complexity and resource consumption.
Solution Approach 2:
The patent combines polynomial processing functionality with the general-purpose processor architecture. The polynomial multiplication and division operations are integrated into the existing instruction set and execution pipeline, merging specialized mathematical operations with general computing resources to avoid duplicating hardware components.
3Adaptability or versatility
If polynomial operations are supported beyond Reed Solomon coding, then versatility is improved, but existing polynomial instructions are insufficient
Solution Approach 1:
The patent implements a comprehensive polynomial instruction set that includes multiplication, division, and remainder operations with configurable polynomial degrees. These universal instructions can support various applications including but not limited to Reed Solomon coding, signal scrambling, and transmission code generation, eliminating the need for application-specific instruction variations.
Solution Approach 2:
The patent enables flexible polynomial operations by allowing dynamic configuration of polynomial parameters (degree, coefficients) through register values and instruction operands. This parameter-based approach allows the same instruction hardware to handle different polynomial types and degrees, providing versatility without increasing structural complexity.
Data Source
AI summary
A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.