Polynomial Evaluation Hardware Logic Rounding Error Reduction
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Solution Overview
Problem
Floating point arithmetic introduces rounding errors when evaluating polynomials, leading to inaccuracies in binary decisions critical for applications like ray tracing in computer graphics, where even trivial errors result in significant visual differences in rendered scenes.
Innovation Solution
A method and system that reduce a set of input polynomials to a minimal set of polynomial components, allowing accurate evaluation using rounded arithmetic by identifying which components cannot be evaluated using other polynomials, and implementing these components in interconnected hardware logic elements to ensure correct zero determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If floating point arithmetic is used to evaluate polynomials in hardware, then a greater range of numbers can be represented, but rounding errors occur leading to inaccuracies in binary decisions
Solution Approach 1:
The polynomial evaluation is divided into multiple terms, each evaluated separately using floating point arithmetic. The results are then combined through addition. This segmentation allows each term to be processed independently, managing the accumulation of rounding errors more effectively than evaluating the entire polynomial as a single operation.
Solution Approach 2:
The patent performs preliminary analysis to determine an optimal evaluation order for the polynomial terms. By reordering terms and performing evaluations in a specific sequence, the patent minimizes the impact of rounding errors before they propagate through subsequent calculations. This preliminary arrangement of operations helps ensure more accurate binary decisions.
2Measurement precision
If more precision bits are added to floating point representation, then rounding errors are reduced, but hardware complexity and power consumption increase
Solution Approach 1:
The patent uses standard precision floating point representations (such as IEEE 754 single or double precision) without adding excessive precision bits. Instead of increasing precision hardware, it applies partial action by carefully selecting which operations require full precision and which can tolerate standard precision, thereby avoiding unnecessary hardware complexity while maintaining sufficient accuracy for binary decisions.
3Device complexity
If standard floating point arithmetic is used, then hardware implementation is simpler, but binary decisions become inaccurate due to rounding errors
Solution Approach 1:
The patent incorporates feedback mechanisms where the results of polynomial evaluations are checked against expected ranges or thresholds. When rounding errors might affect binary decisions, the system uses feedback to detect and correct potential inaccuracies, ensuring reliable outcomes while maintaining simple standard floating point hardware implementation.
Solution Approach 2:
The patent changes operational parameters such as the order of term evaluation and the grouping of operations to optimize accuracy. By modifying these parameters rather than increasing hardware precision, the patent maintains simple hardware implementation while improving the reliability of binary decisions through smarter arithmetic arrangements.
Data Source
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AI summary
An accurate implementation of a polynomial using floating-point or other rounded arithmetic can be generated using a plurality of hardware logic components which each implement an input polynomial such that the zeros in the input polynomial can be determined correctly. The number of different hardware logic components that are used can be reduced by analysing the set of input polynomials and from it generating a set of polynomial components, where each polynomial in the set of input polynomials which is not also in the set of polynomial components, can be generated from a single one of the polynomial components.