Polynomial Interpolation Hardware with Fewer Approximation Regions
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Solution Overview
Problem
Existing methods for generating polynomial interpolation hardware, such as the modified Remez algorithm, fail to minimize the number of polynomials required for accurate approximation, leading to inefficient hardware design, particularly in terms of size and complexity.
Innovation Solution
A two-phase process is employed to generate polynomial interpolation hardware, where the design space is initially populated with feasible designs, and then optimized through iterative removal of polynomial approximations based on user-defined objectives, such as silicon area and processing delay, to minimize hardware complexity and improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a modified Remez algorithm is used to generate polynomial interpolations, then the maximum error in the approximation is minimized, but the number of polynomials is not minimized and hardware size increases
Solution Approach 1:
The invention changes the optimization parameters from minimizing maximum error (Remez algorithm) to minimizing the number of polynomials while maintaining acceptable accuracy. This is achieved by using a genetic algorithm that evolves polynomial sets based on fitness functions evaluating both accuracy and polynomial count, thereby reducing hardware complexity.
Solution Approach 2:
The invention introduces a dynamic optimization process where the polynomial set is iteratively refined through genetic operations (selection, crossover, mutation). The algorithm dynamically adjusts the polynomial configurations across generations to find optimal balances between accuracy and polynomial count, rather than using a static deterministic approach.
2Ease of manufacture
If curve-fitting based approaches are used to generate polynomial interpolations, then the design process is simplified, but the design space is not fully explored and hardware size is not minimized
Solution Approach 1:
The invention implements feedback mechanisms where the fitness function evaluates each polynomial set's performance and feeds this information back to guide the genetic algorithm's evolution. The feedback loop continuously refines the polynomial configurations by selecting, crossing over, and mutating promising candidates, enabling thorough design space exploration while maintaining computational tractability.
Solution Approach 2:
The invention performs preliminary actions by initializing a diverse population of polynomial sets before the optimization begins. This preliminary diversification ensures broad design space coverage from the start, allowing the genetic algorithm to effectively explore and exploit different regions of the solution space without getting trapped in local optima.
3Measurement precision
If more polynomial approximations are used to maintain desired accuracy, then the approximation quality is improved, but the silicon area and processing delay increase
Solution Approach 1:
The invention changes the optimization objective from prioritizing approximation quality to prioritizing hardware efficiency (silicon area and delay). The fitness function is designed to penalize solutions with excessive polynomial counts, thereby evolving polynomial sets that achieve acceptable accuracy with minimal hardware resources.
Solution Approach 2:
The invention applies partial action by using just enough polynomial approximations to meet the desired accuracy threshold, rather than using excessive polynomials. The genetic algorithm identifies the minimal sufficient polynomial sets that satisfy accuracy requirements, eliminating redundant approximations that would increase silicon area and processing delay.
4Measurement precision
If more polynomial approximations are used to maintain desired accuracy, then the approximation quality is improved, but the processing delay increases
Solution Approach 1:
The invention changes the optimization focus from approximation quality to processing speed. The fitness function incorporates processing delay as a penalty term, driving the evolution of polynomial sets that minimize computational steps while maintaining adequate accuracy, thereby reducing processing delay.
Solution Approach 2:
The invention uses partial action by employing the minimum necessary polynomial approximations to achieve acceptable accuracy. By eliminating redundant or overly precise approximations, the solution reduces the number of computational operations required, directly decreasing processing delay while maintaining sufficient approximation quality.
Data Source
AI summary
Examples relate to an apparatus, a device, a method, and a computer program for generating a circuit design of polynomial interpolation hardware. The apparatus comprises processing circuitry configured to sub-divide the range of input values of the polynomial interpolation hardware into a plurality of regions, determine, for each region of the plurality of regions, a set of polynomial approximations that are suitable in view of a desired accuracy of the polynomial interpolation hardware, remove, based on one or more user-defined objectives, polynomial approximations from the respective sets of polynomial approximations, and generate the circuit design of the polynomial interpolation hardware based on one polynomial approximation per region remaining in the respective sets of polynomial approximations after the iterative removal of polynomial approximations.