Polynomial Approximation Kernels With Fixed-Point Compute Graphs
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Solution Overview
Problem
Existing processing units face challenges in balancing latency and throughput, with floating-point units being resource-intensive and power-inefficient, while parallel computing methods are limited by fixed architectures.
Innovation Solution
Automatically generating polynomial-based kernels using scaled fixed-point units within runtime-adjustable interconnected computing grids to approximate functions, minimizing approximation errors while adhering to constraints on accuracy, compute graph size, and hardware utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point units are used to compute functions, then accuracy is improved, but resource consumption and power usage increase
Solution Approach 1:
The patent transforms floating-point computation parameters into fixed-point computation parameters by changing the numerical representation system. This parameter change allows the same computational function to be executed with significantly reduced power consumption while maintaining acceptable accuracy through carefully designed fixed-point arithmetic operations and scaling factors.
Solution Approach 2:
The patent replaces expensive floating-point units with cheaper fixed-point computational units. Fixed-point arithmetic requires simpler hardware circuits that consume less power and occupy fewer resources, making this a cost-effective substitution that trades minimal accuracy loss for substantial resource and power savings.
2Measurement precision
If floating-point units are used to compute functions, then accuracy is improved, but device complexity increases
Solution Approach 1:
The patent changes the computational parameter representation from floating-point to fixed-point format. This parameter transformation simplifies the hardware architecture by eliminating the need for complex floating-point unit circuits, including exponent handling, normalization logic, and specialized ALUs, thereby reducing device complexity while maintaining computational functionality.
Solution Approach 2:
The patent substitutes complex floating-point computational hardware with simpler fixed-point arithmetic units. The fixed-point implementation uses basic integer arithmetic operations that are natively supported by simple ALUs, eliminating the need for dedicated floating-point hardware and significantly reducing overall device complexity.
3Productivity
If parallel computing is implemented, then throughput is improved, but adaptability decreases due to fixed architecture
Solution Approach 1:
The patent introduces dynamic reconfigurability to the parallel computing architecture, allowing the system to adapt its computational structure at runtime. This is achieved through configurable interconnect networks and programmable processing elements that can be dynamically reconfigured to execute different polynomial-based approximation algorithms, combining parallel throughput with runtime adaptability.
Solution Approach 2:
The patent creates a universal parallel computing platform that can execute multiple different polynomial approximation functions through a single reconfigurable architecture. The system uses a family of polynomial-based approximants that can be selectively activated based on the specific computational function required, providing multi-functionality without requiring separate dedicated hardware for each function.
4Use of energy by moving object
If polynomial-based approximation with fixed-point is used, then power consumption is reduced, but approximation error increases
Solution Approach 1:
The patent employs a composite computational approach that combines polynomial-based mathematical approximation with fixed-point arithmetic encoding. This composite method integrates multiple techniques: polynomial series expansion for function approximation, fixed-point scaling for precision control, and iterative refinement to minimize approximation error while maintaining low power consumption throughout the computation pipeline.
Solution Approach 2:
The patent uses truncated polynomial series with a finite number of terms to achieve approximate results rather than exact computation. By carefully selecting the polynomial degree and number of terms, the system achieves sufficient accuracy for the application while performing fewer computational operations, thereby reducing power consumption without significantly compromising the required approximation accuracy.
Data Source
AI summary
An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration. The polynomial-based approximant and its adjusted set of coefficients for which the computed polynomial-based approximant complies with the constraint(s) may be output to one or more processing circuitries configured to approximate the function by computing the polynomial-based approximant.