Polynomial State Mapping for Fractional-Bit Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory technologies face challenges in efficiently mapping between program states and data patterns, particularly in fractional bit per cell configurations, leading to error multiplication and propagation, and often require redundancy and code expansion.
Innovation Solution
The method involves programming groups of memory cells to map combinations of program states to constellation points using a polynomial expression, allowing for systematic assignment of program states to data patterns without adding redundancy, thereby reducing error propagation and maintaining high packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mapping methods are used for fractional bit per cell configurations, then memory storage capacity is achieved, but error multiplication and propagation occur
Solution Approach 1:
The patent segments the mapping process into distinct components: information bits are separated from parity bits, and the mapping is divided into systematic assignment of information bits followed by parity bit calculation. This segmentation reduces error propagation by isolating the impact of mapping errors to specific segments rather than propagating through the entire data structure.
Solution Approach 2:
The patent changes the mapping parameters by using polynomial expressions of order G (where G is the number of memory cells) to determine constellation points. This parameter change enables systematic assignment that reduces error multiplication while maintaining fractional bit per cell efficiency, as the polynomial-based mapping provides a structured approach to assigning program states that minimizes error propagation.
2Reliability
If redundancy and code expansion are added to reduce errors, then reliability improves, but memory capacity and packing density decrease
Solution Approach 1:
The patent applies partial redundancy by calculating parity bits based on the information bits using systematic mapping, rather than adding full redundancy through code expansion. This partial action provides error correction capability while maintaining high packing density, as only the necessary parity information is added rather than excessive redundant data structures.
Solution Approach 2:
The patent changes the approach to error correction by using polynomial-based systematic mapping instead of traditional redundancy-based codes. This parameter change allows the system to achieve reliability through structured parity assignment that maintains high memory capacity, as the polynomial method efficiently generates parity bits without requiring additional redundant storage structures.
3Quantity of substance
If fractional bit per cell configuration is used to increase capacity, then packing density improves, but mapping complexity and error propagation increase
Solution Approach 1:
The patent segments the fractional bit per cell mapping into systematic information bit assignment followed by parity bit calculation. This segmentation simplifies the overall mapping complexity by breaking down the fractional bit mapping process into manageable stages, where information bits are first assigned systematically and then parity bits are calculated to complete the fractional bit representation.
Solution Approach 2:
The patent changes the mapping parameters by using polynomial expressions of order G to determine constellation points for fractional bit per cell configurations. This parameter change provides a structured mathematical approach that simplifies the mapping process while maintaining high packing density, as the polynomial method efficiently handles the fractional bit representation without excessive complexity.
4Ease of manufacture
If conventional mapping is used, then implementation is straightforward, but error multiplication occurs
Solution Approach 1:
The patent changes the mapping parameters by implementing systematic assignment of information bits to constellation points followed by polynomial-based parity calculation. This parameter change maintains implementation simplicity through a structured two-stage process while simultaneously reducing error multiplication, as the systematic assignment provides a clear framework that prevents error propagation through the mapping process.
Data Source
AI summary
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.