Polynomial Modular Reduction Hardware for Cryptoanalysis Resistance
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Solution Overview
Problem
Existing cryptographic algorithms face challenges in securing modular reduction operations of polynomials in finite fields against cryptoanalysis attacks while maintaining speed and accuracy, particularly in resisting power analysis and timing attacks.
Innovation Solution
A computer-implemented method for modular reduction of polynomials in a binary finite field GF(2^n) that estimates the polynomial quotient using a precomputed scaled inverse of the polynomial modulus, injecting random error into the quotient estimation to enhance security and accuracy, utilizing hardware with a random number generator and dedicated computation units for polynomial arithmetic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If deterministic modular reduction is used, then computational speed is improved, but security against cryptoanalysis attacks deteriorates
Solution Approach 1:
The patent applies dynamics by transforming the static, deterministic modular reduction into a dynamic process where random values are introduced at multiple stages. The quotient estimation incorporates random offsets, and the remainder calculation uses dynamically selected random values, making the computational path variable while maintaining mathematical correctness. This dynamic approach preserves speed by using efficient arithmetic operations while preventing cryptographic analysis through unpredictability.
Solution Approach 2:
The patent changes parameters by introducing random variables into the modular reduction algorithm. Specifically, random values are added to the quotient estimation and used in the remainder calculation, transforming the fixed parameter deterministic algorithm into one with variable parameters. This parameter change maintains the mathematical equivalence required for correctness while introducing unpredictability that secures against cryptoanalysis.
2Object-affected harmful factors
If randomized error is injected into quotient estimation, then security is improved, but computational complexity increases
Solution Approach 1:
The patent applies universality by designing a hardware architecture where the same computational units perform both deterministic arithmetic operations and randomized security operations. The modular reduction unit handles both the mathematical reduction and the injection of random values, while the addition units serve both computational and randomization purposes. This multi-functionality reduces overall hardware complexity compared to having separate dedicated circuits for each function.
Solution Approach 2:
The patent applies self-service by having the randomized modular reduction algorithm generate and manage its own random values through integrated random value generation units within the hardware. Rather than requiring external random number generators, the system produces its own random offsets and values internally, simplifying the overall system architecture while maintaining security.
3Object-affected harmful factors
If multiple random values are used in remainder calculation, then security against timing attacks is improved, but number of operations increases
Solution Approach 1:
The patent applies partial action by introducing random values at only the critical stages of the modular reduction process where they provide maximum security benefit, rather than randomizing every operation. Specifically, random offsets are added to the quotient estimation and random values are used in the remainder calculation, while other operations remain deterministic. This selective randomization provides adequate protection against timing attacks while minimizing the increase in computational operations.
Data Source
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AI summary
A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates (32) and randomizes (36) a polynomial quotient q' (x) used for computation of a polynomial remainder. The randomizing error E (x) injected into the approximate polynomial quotient q (x) is limited to a few bits, e.g. less than half a word. The computed (38) polynomial remainder r' (x) is congruent with but a small random multiple of the residue r (x), which can be found by a final strict binary field reduction by the modulus M (x). In addition to a computational unit (10) and operations sequencer (16), the computing hardware also includes a random or pseudo-random number generator (20) for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks.