Polynomial Vector Crypto Processor for Low-Power Post-Quantum Encryption
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Solution Overview
Problem
Existing devices struggle with the computational load and power requirements of post-quantum cryptography, particularly in small IoT devices and PCs, leading to security vulnerabilities and the need for system upgrades, which are costly and inconvenient.
Innovation Solution
A cryptographic processor device that performs post-quantum cryptographic encryption with low power consumption and high speed, utilizing a polynomial memory bank, arithmetic and logic operator, and modular multiplication circuits to handle various encryption protocols efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-quantum cryptographic protocols are implemented using typical microprocessors or microcontrollers, then encryption security is improved, but computational load increases significantly and power consumption rises
Solution Approach 1:
The patent replaces general-purpose microprocessor/microcontroller computation with dedicated cryptographic processor hardware. This substitution of computational mechanics enables post-quantum cryptographic operations to execute at speeds comparable to classical cryptography while consuming similar power, eliminating the performance penalty typically associated with computationally intensive post-quantum algorithms.
Solution Approach 2:
The patent implements configurable cryptographic parameters including adjustable polynomial degrees, modulus values, and transform types (NTT/INTT). This parameter configurability allows optimization of cryptographic operations for different security requirements and performance constraints, enabling the system to adapt between security strength and computational efficiency.
2Reliability
If post-quantum cryptographic protocols are implemented using typical microprocessors or microcontrollers, then encryption security is improved, but power consumption increases
Solution Approach 1:
The patent replaces software-based cryptographic execution on power-constrained microcontrollers with hardware-accelerated cryptographic processor operations. This substitution reduces power consumption by performing cryptographic operations in dedicated hardware circuits rather than through general-purpose processor instruction execution, making post-quantum cryptography viable for battery-powered IoT devices.
3Productivity
If number theoretic transforms are used in cryptographic protocols, then computational efficiency is improved, but memory requirements increase and memory access complexity rises
Solution Approach 1:
The patent combines the NTT and INTT operations into a single integrated hardware circuit that can perform both forward and inverse transforms. This merging eliminates the need for separate transform circuits and reduces memory access complexity by allowing in-place computations and shared resource utilization within the cryptographic processor.
Solution Approach 2:
The patent implements dynamic configurability of transform parameters including transform size, butterfly operation depth, and memory access patterns. This dynamic adaptation allows the NTT/INTT circuit to optimize memory usage based on the specific cryptographic operation being performed, reducing unnecessary memory accesses and simplifying the memory interface.
Data Source
AI summary
The present disclosure provides a cryptographic processor device capable of performing the post-quantum cryptographic encryption with in a high speed with low power, allowing a change of encryption parameters, and handling various cryptographic protocols. The cryptographic processor device executing polynomial vector operations required for a post-quantum cryptography includes: a polynomial memory bank configured to store a plurality of polynomial vectors; and an arithmetic and logic operator configured to perform operation on the polynomial vectors. The arithmetic and logic operator includes a transform operation circuit configured to multiply two polynomial vectors read out from the polynomial memory bank by using a predetermined transform operation including a plurality of operation stages, and including a combined operation unit configured to consecutively perform a first stage operation and a second stage operation among the plurality of operation stages without storing a result of the first operation stage in a memory.