Polynomial Function Verification via Constant kth Difference
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Solution Overview
Problem
Existing methods for formally verifying hardware designs for integrated circuits that implement functions polynomial in one or more input variables face challenges in converging results, especially when dealing with large input domains or complex functions, as they struggle to efficiently verify properties presented in a mathematical manner.
Innovation Solution
The proposed method involves formally verifying that an instantiation of the hardware design has a constant kth difference with respect to the input variable, which significantly reduces the state space needed for verification, allowing for more efficient verification by comparing outputs for similar inputs and focusing on k+1 distinct values, rather than all values in the domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed on all values in the input domain, then verification completeness is improved, but verification time and computational resources increase significantly
Solution Approach 1:
The input domain is segmented into equivalence classes based on the polynomial degree k. Instead of verifying all individual input values, the verification is performed on k+1 representative values from each equivalence class. This segmentation reduces the verification space from the entire input domain to a small subset of representative values while maintaining verification completeness through the mathematical property that polynomial behavior is determined by k+1 points.
Solution Approach 2:
The verification approach changes from checking individual input values to checking the constant kth difference property across the polynomial function. By transforming the verification parameter from input values to the mathematical property of constant differences, the method achieves verification completeness with significantly fewer checks, reducing verification time while maintaining reliability.
2Measurement precision
If the verification method checks all input values, then verification accuracy is improved, but device complexity and computational overhead increase
Solution Approach 1:
The method performs partial verification by checking only k+1 distinct values instead of all input values. This partial action is sufficient to determine polynomial behavior due to the mathematical property that a polynomial of degree k is uniquely determined by k+1 points. The reduced verification set maintains accuracy while significantly lowering computational overhead and device complexity.
Solution Approach 2:
Instead of directly verifying all input values, the method uses a mathematical model (constant kth difference property) as a copy or representation of the polynomial behavior. By verifying this mathematical property on a subset of values, the method infers the behavior for all other values, reducing computational overhead while maintaining verification accuracy through mathematical equivalence.
Data Source
AI summary
Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.