Polyoxide Charge Trapping Layer for Memory Isolation
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Solution Overview
Problem
Conventional charge trapping structures in memory cells rely on thermally grown silicon oxide for electrical isolation, which may not provide sufficient breakdown voltage and conductivity, limiting the performance of memory devices.
Innovation Solution
Employing a polyoxide-based charge trapping component with a tunneling layer, a charge trapping layer, and an amorphous silicon layer that converts into a polyoxide layer through oxidation, offering enhanced electrical isolation and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thermally grown silicon oxide is used for electrical isolation, then the manufacturing process is simple, but the breakdown voltage and conductivity are insufficient
Solution Approach 1:
The patent employs a composite oxide-nitride-oxide (ONO) film structure where a silicon nitride layer is inserted between two oxide layers. This composite structure combines the advantages of oxide layers (good electrical isolation) with the nitrogen layer (enhanced breakdown voltage and conductivity control), thereby improving reliability while maintaining manufacturing feasibility through established semiconductor processing techniques.
Solution Approach 2:
The patent modifies the electrical properties of the isolation layer by changing the composition parameters - specifically incorporating nitrogen into the oxide matrix to form an oxide-nitride-oxide structure. This parameter change enables precise control over breakdown voltage and conductivity characteristics, addressing the insufficiency of conventional thermally grown silicon oxide.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polyoxide layer provides improved breakdown voltage and conductivity, maintaining high isolation dielectric integrity and enabling robust manufacturing processes for memory cells, particularly in dual-bit and multi-bit memory applications.
Implementation Method 1
an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer
Data Source
AI summary
A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.