Polyphase Multi-Phase Clock Generation for Low-Power High-Speed Links
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Solution Overview
Problem
Modern devices, particularly power-constrained devices like battery-powered communication devices, face significant power consumption issues due to aggressive scaling of data rates and corresponding clock speeds, leading to high power consumption.
Innovation Solution
A multi-phase clock generator system that receives an input clock signal and generates N intermediate signals spaced approximately 360/N degrees apart in phase using a poly phase filter, with a phase error corrector reducing phase errors among the signals based on feedback, allowing for higher frequency operations without requiring faster input clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock speeds are increased to achieve higher data rates, then data bandwidth is improved, but power consumption increases significantly
Solution Approach 1:
The patent segments the clock generation function into multiple independent phase generators, each producing a specific phase (0°, 90°, 180°, 270°). This allows the system to generate high-frequency multi-phase clock signals without requiring a single high-speed oscillator, thereby reducing power consumption while maintaining high data bandwidth capability.
Solution Approach 2:
The patent employs dynamic phase adjustment mechanisms where phase shifters can dynamically modify the phase of clock signals based on feedback from phase detectors. This dynamic adaptation enables the system to optimize clock distribution efficiency and reduce unnecessary power consumption while maintaining high data rates.
2Speed
If multi-phase clock signals are generated using a high-frequency oscillator, then operating speed is improved, but power consumption increases
Solution Approach 1:
The patent uses lower-frequency oscillators to generate base clock signals, then performs preliminary phase division and multiplication through digital logic circuits and phase shifters. This preliminary action at lower frequencies reduces power consumption while achieving the required high-speed multi-phase clock outputs through subsequent signal processing stages.
Solution Approach 2:
The patent introduces intermediary components such as phase detectors, feedback circuits, and programmable phase shifters that mediate between the low-frequency oscillator and the high-frequency multi-phase clock outputs. These intermediaries enable frequency multiplication and phase distribution without requiring the oscillator itself to operate at high frequencies, thus reducing power consumption.
3Manufacturing precision
If phase error correction is implemented to improve clock signal accuracy, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal feedback mechanism where a single phase detector and control logic serve multiple phase channels simultaneously. This multi-functional approach enables phase error correction across all four phases (0°, 90°, 180°, 270°) using shared resources, thereby improving phase accuracy without proportionally increasing circuit complexity.
Solution Approach 2:
The patent employs feedback loops where phase detectors continuously monitor phase errors in the generated clock signals and feed this information back to programmable phase shifters for real-time correction. This closed-loop feedback system automatically maintains high phase accuracy without requiring complex manual calibration or additional hardware for each phase channel.
Data Source
AI summary
Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.