Polyphase Clock Generation for Low-Power Accurate Phase Interpolation

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Solution Overview

Problem

Current clock signal generation techniques for high-speed I/O systems face challenges in power consumption, harmonic distortion, and phase linearity, particularly in generating accurate multiphase clock signals for phase rotator-based PLLs, which are essential for maintaining signal integrity and stability in high-resolution phase interpolators.

Innovation Solution

A low-power, highly accurate multiphase clock generation scheme using a combination of phase rotators, phase interpolators, and polyphase filters, specifically a Harmonic Rejection Polyphase Filter (HRPPF) and an 8-phase polyphase filter, to create sinusoidal multiphase clock signals with reduced harmonic distortion and improved phase linearity, enabling efficient clock distribution and sampling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If VCO-based clock signal generation is used, then clock signals can be generated, but power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidoperational stability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent replaces the VCO-based clock generation system with a phase rotator-based system that uses a single reference clock signal. This substitution eliminates the need for multiple VCOs and their associated power consumption while maintaining the required multiphase clock output through phase rotation and interpolation techniques.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If multiphase clock signals are directly delivered from VCO, then clock distribution is simplified, but power consumption increases

Engineering Contradiction:
Improveclock distribution complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent merges the functions of multiple VCOs into a single reference clock source combined with a phase rotator. This consolidation reduces the number of active clock generation devices while maintaining the ability to distribute multiphase clock signals to all required channels, thereby reducing overall power consumption.

Inventive Principle:
Principle #5Merging (Combining)

3Object-generated harmful factors

If low-pass filters are incorporated prior to phase rotators, then harmonic filtering is achieved, but phase linearity is limited

Engineering Contradiction:
Improveharmonic distortionVSAvoidphase linearity
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The patent extracts and removes the problematic low-pass filtering stage from the signal path. Instead of using filters that compromise phase linearity, the design relies on the inherent phase rotation capability and subsequent interpolation to achieve both harmonic reduction and high phase linearity for accurate phase interpolation.

Inventive Principle:
Principle #2Taking out (Extraction)

4Adaptability or versatility

If DLL or ILO is used for multiphase generation, then multiphase clock signals can be created, but area penalty increases

Engineering Contradiction:
Improvemultiphase generation capabilityVSAvoidchip area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements a universal phase rotator-based architecture that can generate any required phase configuration from a single reference clock. This multi-functional approach replaces dedicated DLL or ILO circuits for each channel, significantly reducing the total chip area while maintaining the ability to generate multiphase clock signals as needed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

5Use of energy by moving object

If phase interpolators are used for multiphase generation, then power consumption is reduced, but phase accuracy becomes state-dependent

Engineering Contradiction:
Improvepower consumptionVSAvoidphase accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent introduces a carefully designed phase rotator as an intermediary stage between the reference clock and the phase interpolators. This intermediary ensures that the input signals to the interpolators have optimal phase relationships and minimal harmonic distortion, thereby reducing state-dependent errors and improving overall phase accuracy while maintaining low power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8774336B2Low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters
Publication Date: 2014.07.08 INTEGRATED DEVICE TECH INC
  • US8774336B2 patent drawing
  • US8774336B2 patent drawing
  • US8774336B2 patent drawing

AI summary

Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.