Polyphase Digital Pre-Distortion for Aliasing-Free Amplifier Linearization
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Solution Overview
Problem
Conventional digital pre-distortion systems for linearizing non-linear amplifiers face limitations due to aliasing issues, which can lead to degradation in performance when the bandwidth of the pre-distorted signal exceeds the sample rate, requiring either increased sample rates for the digital pre-distortion module and DAC or impractical processing speeds.
Innovation Solution
The implementation of a polyphase architecture that interpolates the digital input signal by a factor greater than one before pre-distortion and subsequently decimates it to maintain the original sample rate, allowing the digital pre-distortion module to operate at a lower processing speed without increasing the DAC's sample rate, thereby preventing aliasing and improving linearization performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bandwidth of the pre-distorted signal exceeds the sample rate, then the linearization performance degrades due to aliasing, but increasing the sample rate increases the processing speed requirement and DAC complexity
Solution Approach 1:
The pre-distortion processing is segmented into multiple parallel sub-processes operating at lower sample rates. The input signal is divided into multiple channels, each processed independently by separate pre-distortion functions, and then combined to produce the final pre-distorted output. This segmentation allows the system to achieve high effective processing rate without requiring any single DAC to operate at the high sample rate
Solution Approach 2:
The system transitions from a single-dimensional high sample rate approach to a multi-dimensional parallel processing architecture. By distributing the processing across multiple parallel paths operating at lower sample rates, the system achieves the equivalent of high sample rate processing through spatial distribution rather than temporal compression
2Reliability
If the digital pre-distortion module operates at higher processing speed to handle increased sample rates, then aliasing is prevented, but the processing complexity and power consumption increase
Solution Approach 1:
The processing load is segmented across multiple parallel modules operating at lower individual clock rates. Each module processes a portion of the signal at a manageable speed, and the combined output achieves the desired effective processing rate. This divides the energy consumption burden across multiple lower-power units rather than requiring one high-power unit
Solution Approach 2:
Multiple copies of the pre-distortion processing logic are created and operated in parallel at lower sample rates. Instead of one complex high-speed processor, several simpler lower-speed processors are used, each handling a fraction of the total signal, thereby reducing the power consumption of each individual processing unit
Data Source
AI summary
A non-linear amplifier is linearized using interpolation-based digital pre-distortion (DPD). In one embodiment, the digital input signal is interpolated to generate a higher-sample-rate signal that is then pre-distorted. The resulting higher-sample-rate pre-distorted signal is then decimated to generate a final pre-distorted digital signal that is converted into an analog pre-distorted signal by a digital-to-analog converter (DAC) before being applied to the amplifier. In a polyphase embodiment, different versions of the original input digital signal are generated, where each version is then pre-distorted using a different DPD module to generate a different intermediate pre-distorted digital signal. The intermediate pre-distorted signals are filtered and combined to generate the final pre-distorted digital signal. In both embodiments, better linearization (e.g., less aliasing) can be achieved without increasing the sample rate of the DAC and, in the polyphase embodiment, without increasing the processing speed of the DPD modules.