Polyphase Filter Layout for Reconfigurable Oversampled Channelizers
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Solution Overview
Problem
Existing channelizer architectures are inefficient due to layout-based and performance-based issues such as duplicative circuitry, over-reliance on large registers, and underutilized mathematical operators, making them unsuitable for applications requiring dynamic reconfiguration and flexibility in size and power-constrained environments like airborne or spaceborne platforms.
Innovation Solution
A dynamically reconfigurable 2× oversampled channelizer using pipelined stages, polyphase filter, two-phase reorder circuit, FFT circuit, and two-phase merge circuit, allowing for in-field modification of frequency bins and their response, suitable for FPGAs, CPLDs, and ASICs, with reconfigurable parameters like filter coefficients and number of frequency bins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing channelizer architectures are used, then channelization function is provided, but resource duplication and inefficiency occur leading to high computational complexity
Solution Approach 1:
The patent merges multiple channelizer functions into a single reconfigurable architecture that can dynamically adapt to different channelization requirements. The polyphase filter bank and FFT processor are integrated into one system that can be reconfigured via control signals, eliminating the need for multiple separate channelizer circuits and reducing resource duplication.
Solution Approach 2:
The channelizer employs dynamic reconfiguration capabilities where filter coefficients, number of channels, and frequency bin configurations can be changed in real-time through control signals. This dynamic adaptability allows the system to optimize its computational complexity for different operating conditions while maintaining high channelization efficiency.
2Adaptability or versatility
If fixed channelizer configurations are used, then design simplicity is maintained, but adaptability to different frequency ranges and channelization requirements is limited
Solution Approach 1:
The patent creates a universal channelizer architecture that can perform multiple channelization functions across different frequency ranges and resolutions. The single reconfigurable system replaces multiple specialized channelizers, achieving versatility through shared hardware resources controlled by programmable parameters.
Solution Approach 2:
The channelizer achieves adaptability by changing operational parameters such as filter coefficients, number of polyphase sections, and FFT size through control signals. These parameter changes allow the system to adapt to different frequency ranges and channelization requirements without physical reconfiguration, managing complexity through software-controlled parameter adjustment.
3Productivity
If multiple customized channelizers are deployed for different applications, then application-specific optimization is achieved, but size, weight, and power constraints are violated
Solution Approach 1:
The patent implements a single reconfigurable channelizer that can be programmed to optimize performance for different applications including radar, communications, and electronic warfare. This universal approach replaces multiple application-specific channelizers, significantly reducing power consumption while maintaining the ability to achieve application-specific optimization through software configuration.
Data Source
AI summary
Techniques are provided for a polyphase filtering in a dynamically reconfigurable two times (2×) oversampled channelizer. A polyphase filter implementing the techniques according to an embodiment includes a first plurality of dual port memory circuits and a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits. The polyphase filter also includes a second plurality of dual port memory circuits configured to store polyphase filter coefficients and a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. The polyphase filter further includes a multiply circuit configured to perform multiplications of the aligned input data with the polyphase filter coefficients and an adder circuit to sum the results of the multiplications to generate a filtered output.


