Polyphase Filter Clock Recovery for Low Latency Signal Processing
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Solution Overview
Problem
Current clock data recovery methods for high data rate serial transmission protocols face challenges with latency due to feedback loops and are not effective for N-ary serial signals like PAM-N signals, especially under conditions of spread spectrum clocking modulations.
Innovation Solution
The method employs polyphase filters to process input samples in parallel, determining timing parameters directly from these samples without a feedback loop, using difference quantities calculated from time-shifted sets of samples, which allows for real-time processing with reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL based clock data recovery is used, then clock signal recovery is achieved, but latency increases due to feedback loops
Solution Approach 1:
The patent extracts the essential timing information directly from the data signal by detecting edges and determining sampling times, removing the need for a feedback-based PLL loop. This extraction approach eliminates the latency inherent in feedback mechanisms while maintaining reliable clock recovery.
Solution Approach 2:
The patent performs preliminary sampling of the data signal at multiple phases before clock recovery is needed. By pre-determining sampling times and phases in advance, the system avoids the time-consuming feedback iteration of PLL-based methods, achieving low-latency clock recovery.
2Adaptability or versatility
If phase interpolation techniques are used, then frequency shifts are tracked, but latency increases due to feedback control
Solution Approach 1:
The patent uses a form of feedback by comparing phase information from multiple sampled signals to determine optimal sampling times. However, this is a simplified comparison-based feedback rather than a complex PLL feedback loop, achieving frequency shift tracking with reduced latency.
3Device complexity
If blind oversampling is used, then no feedback is required, but larger frequency shifts cannot be handled
Solution Approach 1:
The patent segments the sampling process into multiple phases (first phase, second phase, etc.) with different time shifts. By dividing the sampling into multiple controlled phases rather than single blind sampling, the system can handle larger frequency shifts while maintaining the simplicity of avoiding complex feedback loops.
4Productivity
If polyphase filters process samples in parallel, then real-time processing is achieved, but system complexity increases
Solution Approach 1:
The patent divides the input signal into multiple polyphase components (first polyphase, second polyphase, etc.) that are processed in parallel. This segmentation enables real-time processing by distributing the computational load across multiple simpler filter paths rather than one complex sequential processor.
Solution Approach 2:
The patent combines the results from multiple parallel polyphase filter paths to determine the final timing parameters. By merging the outputs of simpler parallel filters, the system achieves real-time processing capability without requiring any single filter to be overly complex.
Data Source
AI summary
A signal analysis method is described. The signal analysis method includes the following steps. A first difference quantity is determined based on a first set of samples by a first polyphase filter, wherein the first set of samples includes at least two input samples. A second difference quantity is determined based on a second set of samples by a second polyphase filter, wherein the second set of samples includes at least two input samples, wherein the input samples associated with the second set of samples are time-shifted with respect to the input samples associated with the first set of samples. The first difference quantity and the second difference quantity are compared based on a predefined criterion. At least one timing parameter of the symbol sequence is determined based on the comparison of the first difference quantity and the second difference quantity. Further, a signal processing module is described.